Leakage Power Reduction for Battery-Operated Portable Systems
Summary :
This paper addresses bitwidth optimization focusing on leakage power reduction for system-level low-power design. By means of tuning the design parameter, bitwidth tailored to a given application requirements, the datapath width of processors and size of memories are optimized resulting in significant leakage power reduction besides dynamic power reduction. Experimental results for several real embedded applications, show power reduction without performance penalty range from about 21.5% to 66.2% of leakage power, and 14.5% to 59.2% of dynamic power.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.3200-3203
- Publication Date
- 2003/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Power Optimization
Authors
Keyword
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Yun CAO, Hiroto YASUURA, "Leakage Power Reduction for Battery-Operated Portable Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 12, pp. 3200-3203, December 2003, doi: .
Abstract: This paper addresses bitwidth optimization focusing on leakage power reduction for system-level low-power design. By means of tuning the design parameter, bitwidth tailored to a given application requirements, the datapath width of processors and size of memories are optimized resulting in significant leakage power reduction besides dynamic power reduction. Experimental results for several real embedded applications, show power reduction without performance penalty range from about 21.5% to 66.2% of leakage power, and 14.5% to 59.2% of dynamic power.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_3200/_p
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@ARTICLE{e86-a_12_3200,
author={Yun CAO, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Leakage Power Reduction for Battery-Operated Portable Systems},
year={2003},
volume={E86-A},
number={12},
pages={3200-3203},
abstract={This paper addresses bitwidth optimization focusing on leakage power reduction for system-level low-power design. By means of tuning the design parameter, bitwidth tailored to a given application requirements, the datapath width of processors and size of memories are optimized resulting in significant leakage power reduction besides dynamic power reduction. Experimental results for several real embedded applications, show power reduction without performance penalty range from about 21.5% to 66.2% of leakage power, and 14.5% to 59.2% of dynamic power.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Leakage Power Reduction for Battery-Operated Portable Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3200
EP - 3203
AU - Yun CAO
AU - Hiroto YASUURA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - This paper addresses bitwidth optimization focusing on leakage power reduction for system-level low-power design. By means of tuning the design parameter, bitwidth tailored to a given application requirements, the datapath width of processors and size of memories are optimized resulting in significant leakage power reduction besides dynamic power reduction. Experimental results for several real embedded applications, show power reduction without performance penalty range from about 21.5% to 66.2% of leakage power, and 14.5% to 59.2% of dynamic power.
ER -
English
