IEICE TRANSACTIONS on Fundamentals
Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic
Summary :
This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The original contribution of this paper is to evaluate, through actual chip fabrication, the potential impact of multiple-valued current-mode circuit technology on the reduction of hardware complexity required for DSP-oriented programmable ICs. The prototype FPDF fabrication with 0.6 µm CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 71%, respectively, compared with the standard binary logic implementation.
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- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.8 pp.2001-2010
- Publication Date
- 2003/08/01
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on Digital Signal Processing)
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Katsuhiko DEGAWA, Takafumi AOKI, Tatsuo HIGUCHI, "Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 8, pp. 2001-2010, August 2003, doi: .
Abstract: This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The original contribution of this paper is to evaluate, through actual chip fabrication, the potential impact of multiple-valued current-mode circuit technology on the reduction of hardware complexity required for DSP-oriented programmable ICs. The prototype FPDF fabrication with 0.6 µm CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 71%, respectively, compared with the standard binary logic implementation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_8_2001/_p
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@ARTICLE{e86-a_8_2001,
author={Katsuhiko DEGAWA, Takafumi AOKI, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic},
year={2003},
volume={E86-A},
number={8},
pages={2001-2010},
abstract={This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The original contribution of this paper is to evaluate, through actual chip fabrication, the potential impact of multiple-valued current-mode circuit technology on the reduction of hardware complexity required for DSP-oriented programmable ICs. The prototype FPDF fabrication with 0.6 µm CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 71%, respectively, compared with the standard binary logic implementation.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2001
EP - 2010
AU - Katsuhiko DEGAWA
AU - Takafumi AOKI
AU - Tatsuo HIGUCHI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2003
AB - This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The original contribution of this paper is to evaluate, through actual chip fabrication, the potential impact of multiple-valued current-mode circuit technology on the reduction of hardware complexity required for DSP-oriented programmable ICs. The prototype FPDF fabrication with 0.6 µm CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 71%, respectively, compared with the standard binary logic implementation.
ER -
English
