IEICE TRANSACTIONS on Fundamentals
A High Throughput Pipelined Architecture for Blind Adaptive Equalizer with Minimum Latency
Summary :
In this paper, we propose a pipelined architecture for an equalizer based on the Multilevel Modified Constant Modulus Algorithm (MMCMA). We also provide the correction factor that mathematically converts the proposed pipelined adaptive equalizer into an equivalent non-pipelined conventional MMCMA based equalizer. The proposed method of pipelining uses modules with 6 filter coefficients, resulting in an overall latency of a single sampling period, along the main transmission line. The basic concept of the proposed architecture is to implement the Finite Impulse Response (FIR) filter and the algorithm portion of the adaptive equalizer, such that the critical path of the whole circuit has a maximum of three complex multipliers and three adders.
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- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.8 pp.2011-2019
- Publication Date
- 2003/08/01
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- Special Section PAPER (Special Section on Digital Signal Processing)
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Masashi MIZUNO, James OKELLO, Hiroshi OCHI, "A High Throughput Pipelined Architecture for Blind Adaptive Equalizer with Minimum Latency" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 8, pp. 2011-2019, August 2003, doi: .
Abstract: In this paper, we propose a pipelined architecture for an equalizer based on the Multilevel Modified Constant Modulus Algorithm (MMCMA). We also provide the correction factor that mathematically converts the proposed pipelined adaptive equalizer into an equivalent non-pipelined conventional MMCMA based equalizer. The proposed method of pipelining uses modules with 6 filter coefficients, resulting in an overall latency of a single sampling period, along the main transmission line. The basic concept of the proposed architecture is to implement the Finite Impulse Response (FIR) filter and the algorithm portion of the adaptive equalizer, such that the critical path of the whole circuit has a maximum of three complex multipliers and three adders.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_8_2011/_p
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@ARTICLE{e86-a_8_2011,
author={Masashi MIZUNO, James OKELLO, Hiroshi OCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High Throughput Pipelined Architecture for Blind Adaptive Equalizer with Minimum Latency},
year={2003},
volume={E86-A},
number={8},
pages={2011-2019},
abstract={In this paper, we propose a pipelined architecture for an equalizer based on the Multilevel Modified Constant Modulus Algorithm (MMCMA). We also provide the correction factor that mathematically converts the proposed pipelined adaptive equalizer into an equivalent non-pipelined conventional MMCMA based equalizer. The proposed method of pipelining uses modules with 6 filter coefficients, resulting in an overall latency of a single sampling period, along the main transmission line. The basic concept of the proposed architecture is to implement the Finite Impulse Response (FIR) filter and the algorithm portion of the adaptive equalizer, such that the critical path of the whole circuit has a maximum of three complex multipliers and three adders.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - A High Throughput Pipelined Architecture for Blind Adaptive Equalizer with Minimum Latency
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2011
EP - 2019
AU - Masashi MIZUNO
AU - James OKELLO
AU - Hiroshi OCHI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2003
AB - In this paper, we propose a pipelined architecture for an equalizer based on the Multilevel Modified Constant Modulus Algorithm (MMCMA). We also provide the correction factor that mathematically converts the proposed pipelined adaptive equalizer into an equivalent non-pipelined conventional MMCMA based equalizer. The proposed method of pipelining uses modules with 6 filter coefficients, resulting in an overall latency of a single sampling period, along the main transmission line. The basic concept of the proposed architecture is to implement the Finite Impulse Response (FIR) filter and the algorithm portion of the adaptive equalizer, such that the critical path of the whole circuit has a maximum of three complex multipliers and three adders.
ER -
English
