IEICE TRANSACTIONS on Fundamentals
Efficient Block-Level Connectivity Verification Algorithms for Embedded Memories
Summary :
A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if multiple memory blocks are integrated into a single system, the STE approach cannot verify it economically. This paper introduces algorithms for verifying block-level connectivity of memories. The verification time of a large memory can be reduced drastically by using bottom-up verification scheme. That is, a memory block is first verified thoroughly, and then only the interconnection between memory blocks of the large memory needs to be verified. The proposed verification algorithms require (3n+2(
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.12 pp.3185-3192
- Publication Date
- 2004/12/01
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Test
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Jin-Fu LI, "Efficient Block-Level Connectivity Verification Algorithms for Embedded Memories" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 12, pp. 3185-3192, December 2004, doi: .
Abstract: A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if multiple memory blocks are integrated into a single system, the STE approach cannot verify it economically. This paper introduces algorithms for verifying block-level connectivity of memories. The verification time of a large memory can be reduced drastically by using bottom-up verification scheme. That is, a memory block is first verified thoroughly, and then only the interconnection between memory blocks of the large memory needs to be verified. The proposed verification algorithms require (3n+2(
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_12_3185/_p
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@ARTICLE{e87-a_12_3185,
author={Jin-Fu LI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Efficient Block-Level Connectivity Verification Algorithms for Embedded Memories},
year={2004},
volume={E87-A},
number={12},
pages={3185-3192},
abstract={A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if multiple memory blocks are integrated into a single system, the STE approach cannot verify it economically. This paper introduces algorithms for verifying block-level connectivity of memories. The verification time of a large memory can be reduced drastically by using bottom-up verification scheme. That is, a memory block is first verified thoroughly, and then only the interconnection between memory blocks of the large memory needs to be verified. The proposed verification algorithms require (3n+2(
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Efficient Block-Level Connectivity Verification Algorithms for Embedded Memories
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3185
EP - 3192
AU - Jin-Fu LI
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2004
AB - A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if multiple memory blocks are integrated into a single system, the STE approach cannot verify it economically. This paper introduces algorithms for verifying block-level connectivity of memories. The verification time of a large memory can be reduced drastically by using bottom-up verification scheme. That is, a memory block is first verified thoroughly, and then only the interconnection between memory blocks of the large memory needs to be verified. The proposed verification algorithms require (3n+2(
ER -
English
