Most of system-on-chips (SOCs) have many memory cores. Diagnosis is often used to improve the yield of memories. Memory cores usually represent a significant portion of the chip area and dominate the yield of the chip. Memory diagnosis thus is one of key techniques for improving the yield and quality of SOCs. Content addressable memories (CAMs) are important components in many SOCs. In this paper we propose a three-phase diagnosis procedure for binary CAMs (BCAMs). The user can distinguish different types of BCAM-specific comparison and RAM faults and locate the faulty cells with the procedure. A March-like fault identification algorithm is also proposed. The algorithm can distinguish different types of faults--including typical RAM faults and BCAM-specific comparison faults. The algorithm requires 15N Read/Write operations and 2(N + B) Compare operations for an N B-bit BCAM. Analysis results show that the algorithm has 100% diagnostic resolution for the target faults.

In this paper, two techniques for implementing a low-power pipelined analog-to-digital converter (ADC) are proposed. First, the time-interleaved correlated double sampling (CDS) technique is proposed to compensate the finite gain error of operational amplifiers in switched-capacitor circuits without a half-rate front-end sample-and-hold amplifier (SHA). Therefore, low-gain amplifiers and the SHA-less architecture can be used to effectively reduce power consumption of a pipelined ADC. Second, the back-end pipelined stages of a pipelined ADC are implemented using a low-power time-interleaved successive approximation (SA) ADC rather than operational amplifiers to further reduce the power consumption of the proposed pipelined ADC. A 9-bit, 100-MS/s hybrid pipelined-SA ADC is implemented in the TSMC 0.13 µm triple-well 1P8M CMOS process. The ADC achieves a spurious free dynamic range (SFDR) of 62.15 dB and a signal-to-noise distortion ratio (SNDR) of 50.85-dB for 2-MHz input frequency at a 100-MS/s sampling rate. The power consumption is 21.2 mW from a 1.2 V supply. The core area of the ADC is 1.6 mm2.

With the nano-scale technology, an system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes that the complexity of SOC testing is much higher than that of conventional VLSI chip testing. One of the SOC test challenges is the test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than single-code compression schemes. The area cost of the proposed multi-code decompressor is small--only about 3498 µm2 based on TSMC 0.18 µm standard cell technology.

A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if multiple memory blocks are integrated into a single system, the STE approach cannot verify it economically. This paper introduces algorithms for verifying block-level connectivity of memories. The verification time of a large memory can be reduced drastically by using bottom-up verification scheme. That is, a memory block is first verified thoroughly, and then only the interconnection between memory blocks of the large memory needs to be verified. The proposed verification algorithms require (3n+2(log2n+1)+3log2m) Read/Write operations for a 2nm-bit memory, where n and m are the address width and data width, respectively. Also, the algorithms can verify 100% of the inter-port and intra-port signal misplaced faults of the address, data input, and data output ports.

This paper presents an efficient diagnosis scheme for RAMs. Three March-based algorithms are proposed to diagnose simple functional faults of RAMs. A March-15N algorithm is used for locating and partially diagnosing faults of bit-oriented or word-oriented memories, where N represents the address number. Then a 3N March-like algorithm is used for locating the aggressor words (bits) of coupling faults (CFs) in word-oriented (bit-oriented) memories. It also can distinguish the faults which cannot be identified by the March-15N algorithm. Thus, the proposed diagnosis scheme can achieve full diagnosis and locate aggressors with (15N + 3mN) Read/Write operations for a bit-oriented RAM with m CFs. For word-oriented RAMs, a March-like algorithm is also proposed to locate the aggressor bit in the aggressor word with 4 log2B Read/Write operations, where B is the word width. Analysis results show that the proposed diagnosis scheme has higher diagnostic resolution and lower time complexity than the previous fault location and fault diagnosis approaches. A programmable built-in self-diagnosis (BISD) design is also implemented to perform the proposed diagnosis algorithms. Experimental results show that the area overhead of the BISD is small--only about 2.17% and 0.42% for 16 K8-bit and 16 K128-bit SRAMs, respectively.