A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs
Summary :
With the nano-scale technology, an system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes that the complexity of SOC testing is much higher than that of conventional VLSI chip testing. One of the SOC test challenges is the test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than single-code compression schemes. The area cost of the proposed multi-code decompressor is small--only about 3498 µm2 based on TSMC 0.18 µm standard cell technology.
- Publication
- IEICE TRANSACTIONS on Information Vol.E91-D No.10 pp.2428-2434
- Publication Date
- 2008/10/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e91-d.10.2428
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Keyword
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Hong-Ming SHIEH, Jin-Fu LI, "A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 10, pp. 2428-2434, October 2008, doi: 10.1093/ietisy/e91-d.10.2428.
Abstract: With the nano-scale technology, an system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes that the complexity of SOC testing is much higher than that of conventional VLSI chip testing. One of the SOC test challenges is the test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than single-code compression schemes. The area cost of the proposed multi-code decompressor is small--only about 3498 µm2 based on TSMC 0.18 µm standard cell technology.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.10.2428/_p
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@ARTICLE{e91-d_10_2428,
author={Hong-Ming SHIEH, Jin-Fu LI, },
journal={IEICE TRANSACTIONS on Information},
title={A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs},
year={2008},
volume={E91-D},
number={10},
pages={2428-2434},
abstract={With the nano-scale technology, an system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes that the complexity of SOC testing is much higher than that of conventional VLSI chip testing. One of the SOC test challenges is the test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than single-code compression schemes. The area cost of the proposed multi-code decompressor is small--only about 3498 µm2 based on TSMC 0.18 µm standard cell technology.},
keywords={},
doi={10.1093/ietisy/e91-d.10.2428},
ISSN={1745-1361},
month={October},}
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TY - JOUR
TI - A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs
T2 - IEICE TRANSACTIONS on Information
SP - 2428
EP - 2434
AU - Hong-Ming SHIEH
AU - Jin-Fu LI
PY - 2008
DO - 10.1093/ietisy/e91-d.10.2428
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2008
AB - With the nano-scale technology, an system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes that the complexity of SOC testing is much higher than that of conventional VLSI chip testing. One of the SOC test challenges is the test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than single-code compression schemes. The area cost of the proposed multi-code decompressor is small--only about 3498 µm2 based on TSMC 0.18 µm standard cell technology.
ER -
English
