IEICE TRANSACTIONS on Fundamentals
Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints
Summary :
The success in topdown design of recent huge system LSIs is in a seamless transfer of the information resulted from the high level design to the lower level of floorplanning. For the purpose, we introduce a new concept abstract floorplan which is included in the output of high level design. From the abstract floorplan, the pillar blocks are derived which are critical sets of blocks that are expected to determine the width and height of the chip, named the frame. Since the frame and pillar blocks are obtained in the high level stage, they are useful to keep the consistency in the low level physical design if we apply optimization regarding them as constraints. Experiments to MCNC benchmarks showed that abstract floorplanning by pillar blocks output a placement faithful to the one physically optimized block placement with respect to the chip area and the wire-length.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.12 pp.3224-3232
- Publication Date
- 2004/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Floorplan
Authors
Keyword
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Ning FU, Shigetoshi NAKATAKE, Yasuhiro TAKASHIMA, Yoji KAJITANI, "Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 12, pp. 3224-3232, December 2004, doi: .
Abstract: The success in topdown design of recent huge system LSIs is in a seamless transfer of the information resulted from the high level design to the lower level of floorplanning. For the purpose, we introduce a new concept abstract floorplan which is included in the output of high level design. From the abstract floorplan, the pillar blocks are derived which are critical sets of blocks that are expected to determine the width and height of the chip, named the frame. Since the frame and pillar blocks are obtained in the high level stage, they are useful to keep the consistency in the low level physical design if we apply optimization regarding them as constraints. Experiments to MCNC benchmarks showed that abstract floorplanning by pillar blocks output a placement faithful to the one physically optimized block placement with respect to the chip area and the wire-length.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_12_3224/_p
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@ARTICLE{e87-a_12_3224,
author={Ning FU, Shigetoshi NAKATAKE, Yasuhiro TAKASHIMA, Yoji KAJITANI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints},
year={2004},
volume={E87-A},
number={12},
pages={3224-3232},
abstract={The success in topdown design of recent huge system LSIs is in a seamless transfer of the information resulted from the high level design to the lower level of floorplanning. For the purpose, we introduce a new concept abstract floorplan which is included in the output of high level design. From the abstract floorplan, the pillar blocks are derived which are critical sets of blocks that are expected to determine the width and height of the chip, named the frame. Since the frame and pillar blocks are obtained in the high level stage, they are useful to keep the consistency in the low level physical design if we apply optimization regarding them as constraints. Experiments to MCNC benchmarks showed that abstract floorplanning by pillar blocks output a placement faithful to the one physically optimized block placement with respect to the chip area and the wire-length.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3224
EP - 3232
AU - Ning FU
AU - Shigetoshi NAKATAKE
AU - Yasuhiro TAKASHIMA
AU - Yoji KAJITANI
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2004
AB - The success in topdown design of recent huge system LSIs is in a seamless transfer of the information resulted from the high level design to the lower level of floorplanning. For the purpose, we introduce a new concept abstract floorplan which is included in the output of high level design. From the abstract floorplan, the pillar blocks are derived which are critical sets of blocks that are expected to determine the width and height of the chip, named the frame. Since the frame and pillar blocks are obtained in the high level stage, they are useful to keep the consistency in the low level physical design if we apply optimization regarding them as constraints. Experiments to MCNC benchmarks showed that abstract floorplanning by pillar blocks output a placement faithful to the one physically optimized block placement with respect to the chip area and the wire-length.
ER -
English
