A Folded VLSI Architecture of Decision Feedback Equalizer for QAM Modem

Hyeongseok YU; Byung Wook KIM; Jun-Dong CHO

A Folded VLSI Architecture of Decision Feedback Equalizer for QAM Modem

Hyeongseok YU, Byung Wook KIM, Jun-Dong CHO

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In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in VLSI structure using EDA tools due to its regular structure. The method is to employ a time-multiplexed design scheme, so-called Folding, which executes multiple operation on a single functional unit. In addition, we define a new folding set by grouping the adjacent filter taps with data transfer having the same processing sequence between blocks and perform the internal data-bit optimization. By doing so, the computational complexity is reduced by performance optimization and also silicon area is reduced by using a shared operator. Moreover, through the performance and convergence time comparison of the various LMS (e.g. LMS, data signed LMS, error signed LMS, signed-signed LMS) ) coefficient updating algorithms, we identify an optimum LMS algorithm scheme suitable for the low complexity, high performance and high order (64 and 256) QAM applications for the presented Fractionally Spaced Decision Feedback Equalizer. We simulated the proposed design scheme using SYNOPSYS^TM and SPW^TM.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.3 pp.628-639

Publication Date: 2004/03/01

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Type of Manuscript: Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)

Category: Communication Theory and Systems

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Hyeongseok YU, Byung Wook KIM, Jun-Dong CHO, "A Folded VLSI Architecture of Decision Feedback Equalizer for QAM Modem" in IEICE TRANSACTIONS on Fundamentals, vol. E87-A, no. 3, pp. 628-639, March 2004, doi: .
Abstract: In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in VLSI structure using EDA tools due to its regular structure. The method is to employ a time-multiplexed design scheme, so-called Folding, which executes multiple operation on a single functional unit. In addition, we define a new folding set by grouping the adjacent filter taps with data transfer having the same processing sequence between blocks and perform the internal data-bit optimization. By doing so, the computational complexity is reduced by performance optimization and also silicon area is reduced by using a shared operator. Moreover, through the performance and convergence time comparison of the various LMS (e.g. LMS, data signed LMS, error signed LMS, signed-signed LMS) ) coefficient updating algorithms, we identify an optimum LMS algorithm scheme suitable for the low complexity, high performance and high order (64 and 256) QAM applications for the presented Fractionally Spaced Decision Feedback Equalizer. We simulated the proposed design scheme using SYNOPSYS^TM and SPW^TM.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_3_628/_p

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@ARTICLE{e87-a_3_628,
author={Hyeongseok YU, Byung Wook KIM, Jun-Dong CHO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Folded VLSI Architecture of Decision Feedback Equalizer for QAM Modem},
year={2004},
volume={E87-A},
number={3},
pages={628-639},
abstract={In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in VLSI structure using EDA tools due to its regular structure. The method is to employ a time-multiplexed design scheme, so-called Folding, which executes multiple operation on a single functional unit. In addition, we define a new folding set by grouping the adjacent filter taps with data transfer having the same processing sequence between blocks and perform the internal data-bit optimization. By doing so, the computational complexity is reduced by performance optimization and also silicon area is reduced by using a shared operator. Moreover, through the performance and convergence time comparison of the various LMS (e.g. LMS, data signed LMS, error signed LMS, signed-signed LMS) ) coefficient updating algorithms, we identify an optimum LMS algorithm scheme suitable for the low complexity, high performance and high order (64 and 256) QAM applications for the presented Fractionally Spaced Decision Feedback Equalizer. We simulated the proposed design scheme using SYNOPSYS^TM and SPW^TM.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - A Folded VLSI Architecture of Decision Feedback Equalizer for QAM Modem
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 628
EP - 639
AU - Hyeongseok YU
AU - Byung Wook KIM
AU - Jun-Dong CHO
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2004
AB - In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in VLSI structure using EDA tools due to its regular structure. The method is to employ a time-multiplexed design scheme, so-called Folding, which executes multiple operation on a single functional unit. In addition, we define a new folding set by grouping the adjacent filter taps with data transfer having the same processing sequence between blocks and perform the internal data-bit optimization. By doing so, the computational complexity is reduced by performance optimization and also silicon area is reduced by using a shared operator. Moreover, through the performance and convergence time comparison of the various LMS (e.g. LMS, data signed LMS, error signed LMS, signed-signed LMS) ) coefficient updating algorithms, we identify an optimum LMS algorithm scheme suitable for the low complexity, high performance and high order (64 and 256) QAM applications for the presented Fractionally Spaced Decision Feedback Equalizer. We simulated the proposed design scheme using SYNOPSYS^TM and SPW^TM.
ER -