In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in VLSI structure using EDA tools due to its regular structure. The method is to employ a time-multiplexed design scheme, so-called Folding, which executes multiple operation on a single functional unit. In addition, we define a new folding set by grouping the adjacent filter taps with data transfer having the same processing sequence between blocks and perform the internal data-bit optimization. By doing so, the computational complexity is reduced by performance optimization and also silicon area is reduced by using a shared operator. Moreover, through the performance and convergence time comparison of the various LMS (e.g. LMS, data signed LMS, error signed LMS, signed-signed LMS) ) coefficient updating algorithms, we identify an optimum LMS algorithm scheme suitable for the low complexity, high performance and high order (64 and 256) QAM applications for the presented Fractionally Spaced Decision Feedback Equalizer. We simulated the proposed design scheme using SYNOPSYSTM and SPWTM.

A new sorting algorithm and architecture for fast median filter are proposed. This algorithm results in low area VLSI architecture producing low switching activity and without using feedback. The main idea is to employ the extra matrix for fast search operation of rank of oldest window element. We simulated and synthesized this algorithm using SYNOPSYSTM and showed the sufficiency in real time operation.