IEICE TRANSACTIONS on Fundamentals
A Fast Sorting VLSI Architecture for General-Purpose Standard Median Filters
Summary :
A new sorting algorithm and architecture for fast median filter are proposed. This algorithm results in low area VLSI architecture producing low switching activity and without using feedback. The main idea is to employ the extra matrix for fast search operation of rank of oldest window element. We simulated and synthesized this algorithm using SYNOPSYSTM and showed the sufficiency in real time operation.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.3 pp.698-700
- Publication Date
- 2004/03/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on Applications and Implementations of Digital Signal Processing)
- Category
- Image Processing
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Keyword
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Hyeongseok YU, Jun-Dong CHO, "A Fast Sorting VLSI Architecture for General-Purpose Standard Median Filters" in IEICE TRANSACTIONS on Fundamentals,
vol. E87-A, no. 3, pp. 698-700, March 2004, doi: .
Abstract: A new sorting algorithm and architecture for fast median filter are proposed. This algorithm results in low area VLSI architecture producing low switching activity and without using feedback. The main idea is to employ the extra matrix for fast search operation of rank of oldest window element. We simulated and synthesized this algorithm using SYNOPSYSTM and showed the sufficiency in real time operation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_3_698/_p
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@ARTICLE{e87-a_3_698,
author={Hyeongseok YU, Jun-Dong CHO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fast Sorting VLSI Architecture for General-Purpose Standard Median Filters},
year={2004},
volume={E87-A},
number={3},
pages={698-700},
abstract={A new sorting algorithm and architecture for fast median filter are proposed. This algorithm results in low area VLSI architecture producing low switching activity and without using feedback. The main idea is to employ the extra matrix for fast search operation of rank of oldest window element. We simulated and synthesized this algorithm using SYNOPSYSTM and showed the sufficiency in real time operation.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - A Fast Sorting VLSI Architecture for General-Purpose Standard Median Filters
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 698
EP - 700
AU - Hyeongseok YU
AU - Jun-Dong CHO
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2004
AB - A new sorting algorithm and architecture for fast median filter are proposed. This algorithm results in low area VLSI architecture producing low switching activity and without using feedback. The main idea is to employ the extra matrix for fast search operation of rank of oldest window element. We simulated and synthesized this algorithm using SYNOPSYSTM and showed the sufficiency in real time operation.
ER -
English
