A Real-Time Image Compressor Using 2-Dimensional DWT and Its FPGA Implementation

Young-Ho SEO; Wang-Hyun KIM; Ji-Sang YOO; Dai-Gyoung KIM; Dong-Wook KIM

A Real-Time Image Compressor Using 2-Dimensional DWT and Its FPGA Implementation

Young-Ho SEO, Wang-Hyun KIM, Ji-Sang YOO, Dai-Gyoung KIM, Dong-Wook KIM

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This paper proposes the design and implementation of a real-time image compressor using 2-Dimensional Discrete Wavelet Transform (2DDWT), which targets an FPGA as its platform. The image compressor uses Daubechies' bi-orthogonal DWT filters (9, 7) and 16-bit fixed-point data formats for wavelet coefficients in the internal calculation. The target image is NTSC 640240 pixels per field whose color format is Y:Cb:Cr = 4:2:2. We developed for the 2DDWT a new structure with four Multipliers and Accumulators (MACs) for real-time operations. We designed and used a linear fixed scalar quantizer, which includes the exceptional treatment of the coefficients whose absolute values are larger than the quantization region. Only a Huffman entropy encoder was included due to the hardware overhead. The quantizer and Huffman encoder merged into a single functional module. Due to the insufficient memory space of an FPGA, we utilized external memory (SDRAM) as the working and memory storage space. The proposed image compressor maps into an APEX20KC EP20K600CB652-7 from Altera and uses 45% of the Logic Array Block (LAB) and 9% of the Embedded System Block (ESB). With a 33 MHz clock frequency, the proposed image compressor shows a speed of 67 fields per second (33 frames per second), which is more than real-time operation. The resulting image quality from reconstruction is approximately 28 dB in PSNR and its compression ratio is 29:1. Consequently, the proposed image compressor is expected to be used in a dedicated system requiring an image-processing unit.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E87-A No.8 pp.2110-2119

Publication Date: 2004/08/01

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Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

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Young-Ho SEO, Wang-Hyun KIM, Ji-Sang YOO, Dai-Gyoung KIM, Dong-Wook KIM, "A Real-Time Image Compressor Using 2-Dimensional DWT and Its FPGA Implementation" in IEICE TRANSACTIONS on Fundamentals, vol. E87-A, no. 8, pp. 2110-2119, August 2004, doi: .
Abstract: This paper proposes the design and implementation of a real-time image compressor using 2-Dimensional Discrete Wavelet Transform (2DDWT), which targets an FPGA as its platform. The image compressor uses Daubechies' bi-orthogonal DWT filters (9, 7) and 16-bit fixed-point data formats for wavelet coefficients in the internal calculation. The target image is NTSC 640240 pixels per field whose color format is Y:Cb:Cr = 4:2:2. We developed for the 2DDWT a new structure with four Multipliers and Accumulators (MACs) for real-time operations. We designed and used a linear fixed scalar quantizer, which includes the exceptional treatment of the coefficients whose absolute values are larger than the quantization region. Only a Huffman entropy encoder was included due to the hardware overhead. The quantizer and Huffman encoder merged into a single functional module. Due to the insufficient memory space of an FPGA, we utilized external memory (SDRAM) as the working and memory storage space. The proposed image compressor maps into an APEX20KC EP20K600CB652-7 from Altera and uses 45% of the Logic Array Block (LAB) and 9% of the Embedded System Block (ESB). With a 33 MHz clock frequency, the proposed image compressor shows a speed of 67 fields per second (33 frames per second), which is more than real-time operation. The resulting image quality from reconstruction is approximately 28 dB in PSNR and its compression ratio is 29:1. Consequently, the proposed image compressor is expected to be used in a dedicated system requiring an image-processing unit.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e87-a_8_2110/_p

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@ARTICLE{e87-a_8_2110,
author={Young-Ho SEO, Wang-Hyun KIM, Ji-Sang YOO, Dai-Gyoung KIM, Dong-Wook KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Real-Time Image Compressor Using 2-Dimensional DWT and Its FPGA Implementation},
year={2004},
volume={E87-A},
number={8},
pages={2110-2119},
abstract={This paper proposes the design and implementation of a real-time image compressor using 2-Dimensional Discrete Wavelet Transform (2DDWT), which targets an FPGA as its platform. The image compressor uses Daubechies' bi-orthogonal DWT filters (9, 7) and 16-bit fixed-point data formats for wavelet coefficients in the internal calculation. The target image is NTSC 640240 pixels per field whose color format is Y:Cb:Cr = 4:2:2. We developed for the 2DDWT a new structure with four Multipliers and Accumulators (MACs) for real-time operations. We designed and used a linear fixed scalar quantizer, which includes the exceptional treatment of the coefficients whose absolute values are larger than the quantization region. Only a Huffman entropy encoder was included due to the hardware overhead. The quantizer and Huffman encoder merged into a single functional module. Due to the insufficient memory space of an FPGA, we utilized external memory (SDRAM) as the working and memory storage space. The proposed image compressor maps into an APEX20KC EP20K600CB652-7 from Altera and uses 45% of the Logic Array Block (LAB) and 9% of the Embedded System Block (ESB). With a 33 MHz clock frequency, the proposed image compressor shows a speed of 67 fields per second (33 frames per second), which is more than real-time operation. The resulting image quality from reconstruction is approximately 28 dB in PSNR and its compression ratio is 29:1. Consequently, the proposed image compressor is expected to be used in a dedicated system requiring an image-processing unit.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - A Real-Time Image Compressor Using 2-Dimensional DWT and Its FPGA Implementation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2110
EP - 2119
AU - Young-Ho SEO
AU - Wang-Hyun KIM
AU - Ji-Sang YOO
AU - Dai-Gyoung KIM
AU - Dong-Wook KIM
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E87-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2004
AB - This paper proposes the design and implementation of a real-time image compressor using 2-Dimensional Discrete Wavelet Transform (2DDWT), which targets an FPGA as its platform. The image compressor uses Daubechies' bi-orthogonal DWT filters (9, 7) and 16-bit fixed-point data formats for wavelet coefficients in the internal calculation. The target image is NTSC 640240 pixels per field whose color format is Y:Cb:Cr = 4:2:2. We developed for the 2DDWT a new structure with four Multipliers and Accumulators (MACs) for real-time operations. We designed and used a linear fixed scalar quantizer, which includes the exceptional treatment of the coefficients whose absolute values are larger than the quantization region. Only a Huffman entropy encoder was included due to the hardware overhead. The quantizer and Huffman encoder merged into a single functional module. Due to the insufficient memory space of an FPGA, we utilized external memory (SDRAM) as the working and memory storage space. The proposed image compressor maps into an APEX20KC EP20K600CB652-7 from Altera and uses 45% of the Logic Array Block (LAB) and 9% of the Embedded System Block (ESB). With a 33 MHz clock frequency, the proposed image compressor shows a speed of 67 fields per second (33 frames per second), which is more than real-time operation. The resulting image quality from reconstruction is approximately 28 dB in PSNR and its compression ratio is 29:1. Consequently, the proposed image compressor is expected to be used in a dedicated system requiring an image-processing unit.
ER -