IEICE TRANSACTIONS on Fundamentals
Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework
Summary :
Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E103-A No.9 pp.1045-1053
- Publication Date
- 2020/09/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.2019KEP0014
- Type of Manuscript
- Special Section PAPER (Special Section on Circuits and Systems)
- Category
Authors
Foisal AHMED
Nara Institute of Science and Technology (NAIST)
Michihiro SHINTANI
Nara Institute of Science and Technology (NAIST)
Michiko INOUE
Nara Institute of Science and Technology (NAIST)
Keyword
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Foisal AHMED, Michihiro SHINTANI, Michiko INOUE, "Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework" in IEICE TRANSACTIONS on Fundamentals,
vol. E103-A, no. 9, pp. 1045-1053, September 2020, doi: 10.1587/transfun.2019KEP0014.
Abstract: Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2019KEP0014/_p
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@ARTICLE{e103-a_9_1045,
author={Foisal AHMED, Michihiro SHINTANI, Michiko INOUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework},
year={2020},
volume={E103-A},
number={9},
pages={1045-1053},
abstract={Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy.},
keywords={},
doi={10.1587/transfun.2019KEP0014},
ISSN={1745-1337},
month={September},}
Copy
TY - JOUR
TI - Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1045
EP - 1053
AU - Foisal AHMED
AU - Michihiro SHINTANI
AU - Michiko INOUE
PY - 2020
DO - 10.1587/transfun.2019KEP0014
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E103-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2020
AB - Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy.
ER -
English
