Chipless tag systems composed of multimode stepped impedance resonators (SIRs) and a reader based on near-field electromagnetic coupling have been reported. This resonator structure has advantages including a simple design due to its symmetrical structure and good discrimination accuracy because many higher-order mode resonant frequencies can be used for identification of codes. However, in addition to the disadvantage of long resonator length, the frequency response in the tag system becomes unstable due to deterioration of the isolation between the probes because the same probe structure is used for the excitor and detector. In this paper, we propose two methods to solve these problems. One is to adopt an asymmetrical SIR structure with a short-circuited end and open-circuited end, which reduces the resonator length by half while allowing the same number of codes to be generated. The other is to improve isolation between probes by applying different magnetic field and electric field structures to the two probes for excitation and detection. We also examined assignment and identification conditions and clarified that the available number of codes for a unit tag can be more than 15 bits. It becomes clear that a 75-bit chipless tag on a credit card-sized (55×86mm) printed circuit board can be designed by integrating five unit tags.

Matching circuits using LC elements are widely applied to high-frequency circuits such as power amplifier (PA) and low-noise amplifier (LNA). For determining matching condition of multi-stage matching circuits, this paper shows that any multi-stage LC-Ladder matching circuit with resistive termination can be decomposed to the extended L-type matching circuits with resistive termination containing negative elements where the analytical solution exists. The matching conditions of each extended L-type matching circuit are obtained easily from the termination resistances and the design frequency. By synthesizing these simple analysis solutions, it is possible to systematically determine the solution even in a large number of stages (high order) matching circuits.

In IoT (Internet-of-Things) era, the number and variety of hardware devices becomes continuously increasing. Several IoT devices are utilized at infrastructure equipments. How to maintain such IoT devices is a serious concern. Capacitance measurement is one of the powerful ways to detect anomalous states in the structure of the hardware devices. Particularly, measuring capacitance while the hardware device is running is a major challenge but no such researches proposed so far. This paper proposes a capacitance measuring device which measures device capacitance in operation. We firstly combine the AC (alternating current) voltage signal with the DC (direct current) supply voltage signal and generates the fluctuating signal. We supply the fluctuating signal to the target device instead of supplying the DC supply voltage. By effectively filtering the observed current in the target device, the filtered current can be proportional to the capacitance value and thus we can measure the target device capacitance even when it is running. We have implemented the proposed capacitance measuring device on the printed wiring board with the size of 95mm × 70mm and evaluated power consumption and accuracy of the capacitance measurement. The experimental results demonstrate that power consumption of the proposed capacitance measuring device is reduced by 65% in low-power mode from measuring mode and proposed device successfully measured capacitance in 0.002μF resolution.

This paper proposes a technique that increases the lifetime of large scale integration (LSI) devices. As semiconductor technology improves at miniaturizing transistors, aging effects due to bias temperature instability (BTI) seriously affects their lifetime. BTI increases the threshold voltage of transistors thereby also increasing the delay of an electronics device, resulting in failures due to timing violations. To compensate for aging-induced timing violations, we exploit configurable approximate computing. Assuming that target circuits have exact and approximate modes, they are configured for the approximate mode if an aging sensor predicts violations. Experiments using an example circuit revealed an increase in its lifetime to >10 years.

Routing problems derived from silicon-interposer and etc. are often formulated as a set-pair routing problem where the combination of pin-pairs to be connected is flexible. In this routing problem, a length matching routing pattern is often required due to the requirement of the signal propagation delays be the same. We propose a fast length matching routing method for the set-pair routing problem. The existing algorithm generates a good length matching routing pattern in practical time. However, due to the limited searching range, there are length matching routing patterns that cannot find due to the limited searching range of the algorithm. Also, it needs heavy iterative steps to improve a solution, and the computation time is practical but not fast. In the set-pair routing, although pin-pairs to be connected is flexible, it is expected that combinations of pin-pairs which realize length matching are restricted. In our method, such a combination of pin-pairs is selected in advance, then routing is performed to realize the connection of the selected pin-pairs. Heavy iterative steps are not used for both the selection and the routing, then a routing pattern is generated in a short time. In the experiments, we confirm that the quality of routing patterns generated by our method is almost equivalent to the existing algorithm. Furthermore, our method finds length matching routing patterns that the existing algorithm cannot find. The computation time is about 360 times faster than the existing algorithm.

Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy.

Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.

To solve the area and power problems in Finite Impulse Response (FIR) implementations, a faithfully truncated adder-based FIR design is presented in this paper for significant area and power savings while the predefined output accuracy can still be obtained. As a solution to the accuracy loss caused by truncated adders, a static error analysis on the utilization of truncated adders in FIRs was performed. According to the mathematical analysis, we show that, with a given accuracy constraint, the optimal truncated adder configuration for an area-power efficient FIR design can be effortlessly determined. Evaluation results on various FIR implementations by using the proposed faithfully truncated adder designs showed that up to 35.4% and 27.9% savings in area and power consumption can be achieved with less than 1 ulp accuracy loss for uniformly distributed random inputs. Moreover, as a case study for normally distributed signals, a fixed 6-tap FIR is implemented for electrocardiogram (ECG) signal filtering was implemented, in which even with the increased truncated bits up to 10, the mean absolute error (Ē) can be guaranteed to be less than 1 ulp while up to 29.7% and 25.3% savings in area and power can be obtained.

The paper deals with the shortest path-based in-trees on a grid graph. There a root is supposed to move among all vertices. As such a spanning mobility pattern, root trajectories based on a Hamilton path or cycle are discussed. Along such a trajectory, each vertex randomly selects the next hop on the shortest path to the root. Under those assumptions, this paper shows that a root trajectory termed an S-path provides the minimum expected symmetric difference. Numerical experiments show that another trajectory termed a Right-cycle also provides the minimum result.

This paper proposes an active vibration-suppression control method for the systems with multiple disturbances using only the relative displacements and velocities. The controller can suppress the vibration of the main body in the world coordinate, where a velocity disturbance and a force disturbance affect the system simultaneously. The added device plays a similar role as an accelerometer, but we avoid the algebraic loop. The main idea of the feedback law is to convert a nonlinear system into an aseismatic desired system by using the energy shaping technique. A parameter selection procedure is derived by combining the constraints of nonlinear IDA-PBC and the evaluation of the control performance of the linearly approximated system. The effectiveness of the proposed method is confirmed by simulations for an example.

Various types of synchronization phenomena have been reported in coupled chaotic systems. In recent years, the applications of these phenomena have been advancing for utilization in sensor network systems, secure communication systems, and biomedical systems. Specifically, chaos-chaos intermittency (CCI) synchronization is a characterized synchronization phenomenon. Previously, we proposed a new chaos control method, termed as the “reduced region of orbit (RRO) method,” to achieve CCI synchronization using external feedback signals. This method has been gathering research attention because of its ability to induce CCI synchronization; this can be achieved even if internal system parameters cannot be adjusted by external factors. Further, additive stochastic noise is known to have a similar effect. The objective of this study was to compare the performance of the RRO method and the method that applies stochastic noise, both of which are capable of inducing CCI synchronization. The results showed that even though CCI synchronization can be realized using both control methods under the induced attractor merging condition, the RRO method possesses higher adoptability and accomplishes a higher degree of CCI synchronization compared to additive stochastic noise. This advantage might facilitate the application of synchronization in coupled chaotic systems.

In this paper, we propose a filter-and-forward relay scheme with energy harvesting for single-carrier transmission in frequency-selective channels. The relay node harvests energy from both the source node transmit signal and its own transmit signal by self-energy recycling. The signal received by the relay node is filtered to suppress the inter-symbol interference and then forwarded to the destination node using the harvested energy. We consider a filter design method based on the signal-to-interference-plus-noise power ratio maximization, subject to a constraint that limits the relay transmit power. In addition, we provide a golden-section search based algorithm to optimize the power splitting ratio of the power splitting protocol. The simulation results show that filtering and self-energy recycling of the proposed scheme are effective in improving performance. It is also shown that the proposed scheme is useful even when only partial channel state information is available.

A polyphase sequence set with orthogonality consisting complex elements with unit magnitude, can be expressed by a unitary matrix corresponding to the complex Hadamard matrix or the discrete Fourier transform (DFT) matrix, whose rows are orthogonal to each other. Its matched filter bank (MFB), which can simultaneously output the correlation between a received symbol and any sequence in the set, is effective for constructing communication systems flexibly. This paper discusses the compact design of the MFB of a polyphase sequence set, which can be applied to any sequence set generated by the given logic function. It is primarily focused on a ZCZ code with q-phase or more elements expressed as A(N=q^n+s, M=q^n-1, Zcz=q^s(q-1)), where q, N, M and Zcz respectively denote, a positive integer, sequence period, family size, and a zero correlation zone, since the compact design of the MFB becomes difficult when Zcz is large. It is shown that the given logic function on the ring of integers modulo q generating the ZCZ code gives the matrix representation of the MFB that M-dimensional output vector can be represented by the product of the unitary matrix of order M and an M-dimensional input vector whose elements are written as the sum of elements of an N-dimensional input vector. Since the unitary matrix (complex Hadamard matrix) can be factorized into n-1 unitary matrices of order M with qM nonzero elements corresponding to fast unitary transform, a compact MFB with a minimum number of circuit elements can be designed. Its hardware complexity is reduced from O(MN) to O(qM log _q M+N).

This paper describes designing a new pedestrian navigation system using a comprehensive framework called the pedestrian navigation concept reference model (PNCRM). We implement this system as a publicly-available smartphone application and evaluate its positioning performance near Omiya station's western entrance. We also evaluate users' subjective impressions of the system using a questionnaire. In both cases, promising results are obtained, showing that the PNCRM can be used as a tool for designing pedestrian navigation systems, allowing such systems to be created systematically.

Broadband amplifiers have been used in modern wireless communication systems. However, the accompanying disadvantage is that there is more nonlinear interference in the available operating frequency band. In addition to the in-band intermodulation distortion which affecting adjacent frequency bands the most important is harmonic distortion. In this letter we present a robust and low complex digital harmonic canceling model called cross-disturbing harmonic (CDH) model for broadband power amplifiers (PAs). The approach introducing cross terms is used to enhance the robustness of the model, thereby significantly increase the stability of the system. The CDH model still has excellent performance when actively reducing the number of coefficients. Comparisons are conducted between the CDH model and the other state-of-the-art model called memory polynomial harmonic (MPM) model. Experimental results show that the CDH model can achieve comparable performance as the MPM model but with much fewer (43%) coefficients.

Simultaneous multithreading technology (SMT) can effectively improve the overall throughput and fairness through improving the resources usage efficiency of processors. Traditional works have proposed some metrics for evaluation in real systems, each of which strikes a trade-off between fairness and throughput. How to choose an appropriate metric to meet the demand is still controversial. Therefore, we put forward suggestions on how to select the appropriate metrics through analyzing and comparing the characteristics of each metric. In addition, for the new application scenario of cloud computing, the data centers have high demand for the quality of service for killer applications, which bring new challenges to SMT in terms of performance guarantees. Therefore, we propose a new metric P-slowdown to evaluate the quality of performance guarantees. Based on experimental data, we show the feasibility of P-slowdown on performance evaluation. We also demonstrate the benefit of P-slowdown through two use cases, in which we not only improve the performance guarantee level of SMT processors through the cooperation of P-slowdown and resources allocation strategy, but also use P-slowdown to predict the occurrence of abnormal behavior against security attacks.