Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules

Yi GUO; Heming SUN; Ping LEI; Shinji KIMURA

doi:10.1587/transfun.2019KEP0002

IEICE TRANSACTIONS on Fundamentals

Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules

Yi GUO, Heming SUN, Ping LEI, Shinji KIMURA

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Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E103-A No.9 pp.1054-1062

Publication Date: 2020/09/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.2019KEP0002

Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems)

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Authors

Yi GUO
  Waseda University
Heming SUN
  the Waseda Research Institute for Science and Engineering,PRESTO
Ping LEI
  Waseda University
Shinji KIMURA
  Waseda University

Keyword

approximate computing, FPGA-based, multiplier, low-power design

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Yi GUO, Heming SUN, Ping LEI, Shinji KIMURA, "Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules" in IEICE TRANSACTIONS on Fundamentals, vol. E103-A, no. 9, pp. 1054-1062, September 2020, doi: 10.1587/transfun.2019KEP0002.
Abstract: Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2019KEP0002/_p

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@ARTICLE{e103-a_9_1054,
author={Yi GUO, Heming SUN, Ping LEI, Shinji KIMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules},
year={2020},
volume={E103-A},
number={9},
pages={1054-1062},
abstract={Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.},
keywords={},
doi={10.1587/transfun.2019KEP0002},
ISSN={1745-1337},
month={September},}

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TY - JOUR
TI - Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1054
EP - 1062
AU - Yi GUO
AU - Heming SUN
AU - Ping LEI
AU - Shinji KIMURA
PY - 2020
DO - 10.1587/transfun.2019KEP0002
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E103-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2020
AB - Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.
ER -

IEICE TRANSACTIONS on Fundamentals