IEICE TRANSACTIONS on Fundamentals
An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM
Summary :
In this paper, we present an analysis of local variability of bias temperature instability (BTI) by measuring Ring-Oscillators (RO) on various processes and its impact on logic circuit and SRAM. The evaluation results based on measuring ROs of a test elementary group (TEG) fabricated in 7nm Fin Field Effect Transistor (FinFET) process, 16/14nm generation FinFET processes and a 28nm planer process show that the standard deviations of Negative BTI (NBTI) Vth degradation (σ(ΔVthp)) are proportional to the square root of the mean value (µ(ΔVthp)) at any stress time, Vth flavors and various recovery conditions. While the amount of local BTI variation depends on the gate length, width and number of fins, the amount of local BTI variation at the 7nm FinFET process is slightly larger than other processes. Based on these measurement results, we present an analysis result of its impact on logic circuit considering measured Vth dependency on global NBTI in the 7nm FinFET process. We also analyse its impact on SRAM minimum operation voltage (Vmin) of static noise margin (SNM) based on sensitivity analysis and shows non-negligible Vmin degradation caused by local NBTI.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E104-A No.11 pp.1536-1545
- Publication Date
- 2021/11/01
- Publicized
- 2021/05/25
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.2020KEP0017
- Type of Manuscript
- Special Section PAPER (Special Section on Circuits and Systems)
- Category
Authors
Mitsuhiko IGARASHI
Renesas Electronics Corporation,Kyoto Institute of Technology
Yuuki UCHIDA
Renesas Electronics Corporation
Yoshio TAKAZAWA
Renesas Electronics Corporation
Makoto YABUUCHI
Renesas Electronics Corporation
Yasumasa TSUKAMOTO
Renesas Electronics Corporation
Koji SHIBUTANI
Renesas Electronics Corporation
Kazutoshi KOBAYASHI
Kyoto Institute of Technology
Keyword
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Mitsuhiko IGARASHI, Yuuki UCHIDA, Yoshio TAKAZAWA, Makoto YABUUCHI, Yasumasa TSUKAMOTO, Koji SHIBUTANI, Kazutoshi KOBAYASHI, "An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM" in IEICE TRANSACTIONS on Fundamentals,
vol. E104-A, no. 11, pp. 1536-1545, November 2021, doi: 10.1587/transfun.2020KEP0017.
Abstract: In this paper, we present an analysis of local variability of bias temperature instability (BTI) by measuring Ring-Oscillators (RO) on various processes and its impact on logic circuit and SRAM. The evaluation results based on measuring ROs of a test elementary group (TEG) fabricated in 7nm Fin Field Effect Transistor (FinFET) process, 16/14nm generation FinFET processes and a 28nm planer process show that the standard deviations of Negative BTI (NBTI) Vth degradation (σ(ΔVthp)) are proportional to the square root of the mean value (µ(ΔVthp)) at any stress time, Vth flavors and various recovery conditions. While the amount of local BTI variation depends on the gate length, width and number of fins, the amount of local BTI variation at the 7nm FinFET process is slightly larger than other processes. Based on these measurement results, we present an analysis result of its impact on logic circuit considering measured Vth dependency on global NBTI in the 7nm FinFET process. We also analyse its impact on SRAM minimum operation voltage (Vmin) of static noise margin (SNM) based on sensitivity analysis and shows non-negligible Vmin degradation caused by local NBTI.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2020KEP0017/_p
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@ARTICLE{e104-a_11_1536,
author={Mitsuhiko IGARASHI, Yuuki UCHIDA, Yoshio TAKAZAWA, Makoto YABUUCHI, Yasumasa TSUKAMOTO, Koji SHIBUTANI, Kazutoshi KOBAYASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM},
year={2021},
volume={E104-A},
number={11},
pages={1536-1545},
abstract={In this paper, we present an analysis of local variability of bias temperature instability (BTI) by measuring Ring-Oscillators (RO) on various processes and its impact on logic circuit and SRAM. The evaluation results based on measuring ROs of a test elementary group (TEG) fabricated in 7nm Fin Field Effect Transistor (FinFET) process, 16/14nm generation FinFET processes and a 28nm planer process show that the standard deviations of Negative BTI (NBTI) Vth degradation (σ(ΔVthp)) are proportional to the square root of the mean value (µ(ΔVthp)) at any stress time, Vth flavors and various recovery conditions. While the amount of local BTI variation depends on the gate length, width and number of fins, the amount of local BTI variation at the 7nm FinFET process is slightly larger than other processes. Based on these measurement results, we present an analysis result of its impact on logic circuit considering measured Vth dependency on global NBTI in the 7nm FinFET process. We also analyse its impact on SRAM minimum operation voltage (Vmin) of static noise margin (SNM) based on sensitivity analysis and shows non-negligible Vmin degradation caused by local NBTI.},
keywords={},
doi={10.1587/transfun.2020KEP0017},
ISSN={1745-1337},
month={November},}
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TY - JOUR
TI - An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1536
EP - 1545
AU - Mitsuhiko IGARASHI
AU - Yuuki UCHIDA
AU - Yoshio TAKAZAWA
AU - Makoto YABUUCHI
AU - Yasumasa TSUKAMOTO
AU - Koji SHIBUTANI
AU - Kazutoshi KOBAYASHI
PY - 2021
DO - 10.1587/transfun.2020KEP0017
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E104-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2021
AB - In this paper, we present an analysis of local variability of bias temperature instability (BTI) by measuring Ring-Oscillators (RO) on various processes and its impact on logic circuit and SRAM. The evaluation results based on measuring ROs of a test elementary group (TEG) fabricated in 7nm Fin Field Effect Transistor (FinFET) process, 16/14nm generation FinFET processes and a 28nm planer process show that the standard deviations of Negative BTI (NBTI) Vth degradation (σ(ΔVthp)) are proportional to the square root of the mean value (µ(ΔVthp)) at any stress time, Vth flavors and various recovery conditions. While the amount of local BTI variation depends on the gate length, width and number of fins, the amount of local BTI variation at the 7nm FinFET process is slightly larger than other processes. Based on these measurement results, we present an analysis result of its impact on logic circuit considering measured Vth dependency on global NBTI in the 7nm FinFET process. We also analyse its impact on SRAM minimum operation voltage (Vmin) of static noise margin (SNM) based on sensitivity analysis and shows non-negligible Vmin degradation caused by local NBTI.
ER -
English
