As a mobile phone progresses with the third, fourth, and fifth generations, the frequency bands used in mobile phones are increasing dramatically. RF components for mobile phone terminals correspond to this increasing frequency band. In the case of power amplifier (PA), which is one of the RF components, it is necessary to correspond many frequency bands in one PA. In this case, the wideband of the matching circuit is a typical one of the technical problems of PA. In this study, we focus on two-stage and three-stage connections of LC ladder matching circuits widely applied in PA, and compare them from the viewpoint of broadband. In order to efficiently analyze multi-stage LC-matching circuits, the following two new methods were devised. First, we derived the analysis formula of LC and CL-matching circuits when the termination impedance was extended to a complex number. Second, we derived a condition in which the frequency derivative of the input impedance is zero.

This paper proposes a switched pinning control method with a multi-rating mechanism for vehicle platoons. The platoons are expressed as multi-agent systems consisting of mass-damper systems in which pinning agents receive target velocities from external devices (ex. intelligent traffic signals). We construct model predictive control (MPC) algorithm that switches pinning agents via mixed-integer quadratic programmings (MIQP) problems. The optimization rate is determined according to the convergence rate to the target velocities and the inter-vehicular distances. This multi-rating mechanism can reduce the computational load caused by iterative calculation. Numerical results demonstrate that our method has a reduction effect on the string instability by selecting the pinning agents to minimize errors of the inter-vehicular distances to the target distances.

This paper addresses distributed optimal estimation over wireless sensor networks with scalable communications. For realizing scalable communication, a data-aggregation method is introduced. Since our previously proposed method cannot guarantee the global optimality of each estimator, a modified protocol is proposed. A modification of the proposed method is that weights are introduced in the data aggregation. For selecting the weight values in the data aggregation, a redundant output reduction method with minimum covariance is discussed. Based on the proposed protocol, all estimators can calculate the optimal estimate. Finally, numerical simulations show that the proposed method can realize both the scalability of communication and high accuracy estimation.

With the rapid progress of the integrated nanophotonics technology, the optical neural network architecture has been widely investigated. Since the optical neural network can complete the inference processing just by propagating the optical signal in the network, it is expected more than one order of magnitude faster than the electronics-only implementation of artificial neural networks (ANN). In this paper, we first propose an optical vector-matrix multiplication (VMM) circuit using wavelength division multiplexing, which enables inference processing at the speed of light with ultra-wideband. This paper next proposes optoelectronic circuit implementation for batch normalization and activation function, which significantly improves the accuracy of the inference processing without sacrificing the speed performance. Finally, using a virtual environment for machine learning and an optoelectronic circuit simulator, we demonstrate the ultra-fast and accurate operation of the optical-electronic ANN circuit.

Hardware accelerators are designed to support a specialized processing dataflow for everchanging deep neural networks (DNNs) under various processing environments. This paper introduces two hardware properties to describe the cost of data movement in each memory hierarchy. Based on the hardware properties, this paper proposes a set of evaluation metrics that are able to evaluate the number of memory accesses and the required memory capacity according to the specialized processing dataflow. Proposed metrics are able to analytically predict energy, throughput, and area of a hardware design without detailed implementation. Once a processing dataflow and constraints of hardware resources are determined, the proposed evaluation metrics quickly quantify the expected hardware benefits, thereby reducing design time.

We propose an algorithm for the constrained design of FIR filters with sparse coefficients. In general filter design approaches, as the length of the filter increases, the number of multipliers used to construct the filter increases. This is a serious problem, especially in two-dimensional FIR filter designs. The FIR filter coefficients designed by the least-squares method with peak error constraint are optimal in the sense of least-squares within a given order, but not necessarily optimal in terms of constructing a filter that meets the design specification under the constraints on the number of coefficients. That is, a higher-order filter with several zero coefficients can construct a filter that meets the specification with a smaller number of multipliers. We propose a two-step approach to design constrained sparse FIR filters. Our method minimizes the number of non-zero coefficients while the frequency response of the filter that meets the design specification. It achieves better performance in terms of peak error than conventional constrained least-squares designs with the same or higher number of multipliers in both one-dimensional and two-dimensional filter designs.

Accumulate Repeat-4 Jagged-Accumulate (AR4JA) codes, which are channel codes designed for deep-space communications, are a series of QC-LDPC codes. Structures of these codes' generator matrix can be exploited to design reconfigurable encoders. To make the decoder reconfigurable and achieve shorter convergence time, turbo-like decoding message passing (TDMP) is chosen as the hardware decoder's decoding schedule and normalized min-sum algorithm (NMSA) is used as decoding algorithm to reduce hardware complexity. In this paper, we propose a reconfigurable decoder and present its FPGA implementation results. The decoder can achieve throughput greater than 74 Mbps.

Due to the rapid growth of the information industry, various Internet of Things (IoT) devices have been widely used in our daily lives. Since the demand for low-cost and high-performance hardware devices has increased, malicious third-party vendors may insert malicious circuits into the products to degrade their performance or to leak secret information stored at the devices. The malicious circuit surreptitiously inserted into the hardware products is known as a ‘hardware Trojan.’ How to detect hardware Trojans becomes a significant concern in recent hardware production. In this paper, we propose a hardware Trojan detection method that employs two-stage neural networks and effectively utilizes the Trojan probability of neighbor nets. At the first stage, the 11 Trojan features are extracted from the nets in a given netlist, and then we estimate the Trojan probability that shows the probability of the Trojan nets. At the second stage, we learn the Trojan probability of the neighbor nets for each net in the netlist and classify the nets into a set of normal nets and Trojan ones. The experimental results demonstrate that the average true positive rate becomes 83.6%, and the average true negative rate becomes 96.5%, which is sufficiently high compared to the existing methods.

The binary quadratic knapsack problem (QKP) aims at optimizing a quadratic cost function within a single knapsack. Its applications and difficulty make it appealing for various industrial fields. In this paper we present an efficient strategy to solve the problem by modeling it as an Ising spin model using an Ising machine to search for its ground state which translates to the optimal solution of the problem. Secondly, in order to facilitate the search, we propose a novel technique to visualize the landscape of the search and demonstrate how difficult it is to solve QKP on an Ising machine. Finally, we propose two software solution improvement algorithms to efficiently solve QKP on an Ising machine.

In this paper, we present an analysis of local variability of bias temperature instability (BTI) by measuring Ring-Oscillators (RO) on various processes and its impact on logic circuit and SRAM. The evaluation results based on measuring ROs of a test elementary group (TEG) fabricated in 7nm Fin Field Effect Transistor (FinFET) process, 16/14nm generation FinFET processes and a 28nm planer process show that the standard deviations of Negative BTI (NBTI) V_th degradation (σ(ΔV_thp)) are proportional to the square root of the mean value (µ(ΔV_thp)) at any stress time, V_th flavors and various recovery conditions. While the amount of local BTI variation depends on the gate length, width and number of fins, the amount of local BTI variation at the 7nm FinFET process is slightly larger than other processes. Based on these measurement results, we present an analysis result of its impact on logic circuit considering measured V_th dependency on global NBTI in the 7nm FinFET process. We also analyse its impact on SRAM minimum operation voltage (V_min) of static noise margin (SNM) based on sensitivity analysis and shows non-negligible V_min degradation caused by local NBTI.

Optical logic circuits based on integrated nanophotonics attract significant interest due to their ultra-high-speed operation. However, the power dissipation of conventional optical logic circuits is exponential to the number of inputs of target logic functions. This paper proposes a synthesis method reducing power dissipation to a polynomial order of the number of inputs while exploiting the high-speed nature. Our method divides the target logic function into multiple sub-functions with Optical-to-Electrical (OE) converters. Each sub-function has a smaller number of inputs than that of the original function, which enables to exponentially reduce the power dissipated by an optical logic circuit representing the sub-function. The proposed synthesis method can mitigate the OE converter delay overhead by parallelizing sub-functions. We apply the proposed synthesis method to the ISCAS'85 benchmark circuits. The power consumption of the conventional circuits based on the Binary Decision Diagram (BDD) is at least three orders of magnitude larger than that of the optical logic circuits synthesized by the proposed method. The proposed method reduces the power consumption to about 100mW. The delay of almost all the circuits synthesized by the proposed method is kept less than four times the delay of the conventional BDD-based circuit.

With the widespread use of Internet of Things (IoT) devices in recent years, we utilize a variety of hardware devices in our daily life. On the other hand, hardware security issues are emerging. Power analysis is one of the methods to detect anomalous behaviors, but it is hard to apply it to IoT devices where an operating system and various software programs are running. In this paper, we propose an anomalous behavior detection method for an IoT device by extracting application-specific power behaviors. First, we measure power consumption of an IoT device, and obtain the power waveform. Next, we extract an application-specific power waveform by eliminating a steady factor from the obtained power waveform. Finally, we extract feature values from the application-specific power waveform and detect an anomalous behavior by utilizing the local outlier factor (LOF) method. We conduct two experiments to show how our proposed method works: one runs three application programs and an anomalous application program randomly and the other runs three application programs in series and an anomalous application program very rarely. Application programs on both experiments are implemented on a single board computer. The experimental results demonstrate that the proposed method successfully detects anomalous behaviors by extracting application-specific power behaviors, while the existing approaches cannot.

A method for runtime energy optimization based on the supply voltage (V_dd) and the threshold voltage (V_th) scaling is proposed. This paper refers to the optimal voltage pair, which minimizes the energy consumption of LSI circuits under a target delay constraint, as a Minimum Energy Point (MEP). The MEP dynamically fluctuates depending on the operating conditions determined by a target delay constraint, an activity factor and a chip temperature. In order to track the MEP, this paper proposes a closed-form continuous function that determines the MEP over a wide operating performance region ranging from the above-threshold region down to the sub-threshold region. Based on the MEP determination formula, an MEP tracking algorithm is also proposed. The MEP tracking algorithm estimates the MEP even though the operating conditions widely change. Measurement results based on a 32-bit RISC processor fabricated in a 65-nm Silicon On Thin Buried oxide (SOTB) process technology show that the proposed method estimates the MEP within a 5% energy loss in comparison with the actual MEP operation.

This study has developed a system that performs data communications using high frequency bands of sound signals. Unlike radio communication systems using advanced wireless devices, it only requires the legacy devices such as microphones and speakers employed in ordinary telephony communication systems. In this study, we have investigated the possibility of a machine learning approach to improve the recognition accuracy identifying binary symbols exchanged through sound media. This paper describes some experimental results evaluating the performance of our proposed technique employing a neural network as its classifier of binary symbols. The experimental results indicate that the proposed technique may have a certain appropriateness for designing an optimal classifier for the symbol identification task.

This paper investigates an adaptive notch digital filter that employs normal state-space realization of a single-frequency second-order IIR notch digital filter. An adaptive algorithm is developed to minimize the mean-squared output error of the filter iteratively. This algorithm is based on a simplified form of the gradient-decent method. Stability and frequency estimation bias are analyzed for the adaptive iterative algorithm. Finally, a numerical example is presented to demonstrate the validity and effectiveness of the proposed adaptive notch digital filter and the frequency-estimation bias analyzed for the adaptive iterative algorithm.

The Smith method has been used to control physical plants with dead time components, where plant states after the dead time is elapsed are predicted and a control input is determined based on the predicted states. We extend the method to the symbolic control and design a symbolic Smith controller to deal with a nondeterministic embedded system. Due to the nondeterministic transitions, the proposed controller computes all reachable plant states after the dead time is elapsed and determines a control input that is suitable for all of them in terms of a given control specification. The essence of the Smith method is that the effects of the dead time are suppressed by the prediction, however, which is not always guaranteed for nondeterministic systems because there may exist no control input that is suitable for all predicted states. Thus, in this paper, we discuss the existence of a deadlock-free symbolic Smith controller. If it exists, it is guaranteed that the effects of the dead time can be suppressed and that the controller can always issue the control input for any reachable state of the plant. If it does not exist, it is proved that the deviation from the control specification is essentially inevitable.

In this paper, we explore the security against integral attacks on well-known stream ciphers SNOW 3G and KCipher-2. SNOW 3G is the core of the 3GPP confidentiality and integrity algorithms UEA2 and UIA2, and KCipher-2 is a standard algorithm of ISO/IEC 18033-4 and CRYPTREC. Specifically, we investigate the propagation of the division property inside SNOW 3G and KCipher-2 by the Mixed-Integer Linear Programming to efficiently find an integral distinguisher. As a result, we present a 7-round integral distinguisher with 2³ chosen IVs for KCipher-2. As far as we know, this is the first attack on a reduced variant of KCipher-2 by the third party. In addition, we present a 13-round integral distinguisher with 2⁷ chosen IVs for SNOW 3G, whose time/data complexity is half of the previous best attack by Biryukov et al.

Permutation polynomials over finite fields have been widely studied due to their important applications in mathematics and cryptography. In recent years, 2-to-1 mappings over finite fields were proposed to build almost perfect nonlinear functions, bent functions, and the semi-bent functions. In this paper, we generalize the 2-to-1 mappings to m-to-1 mappings, including their construction methods. Some applications of m-to-1 mappings are also discussed.

This paper proposes a new class of signature codes for synchronous optical code-division multiple access (CDMA) and describes a general method for construction of the codes. The proposed codes can be obtained from generalized modified prime sequence codes (GMPSCs) based on extension fields GF(q), where q=p^m, p is a prime number, and m is a positive integer. It has been reported that optical CDMA systems using GMPSCs remove not only multi-user interference but also optical interference (e.g., background light) with a constant intensity during a slot of length q². Recently, the authors have reported that optical CDMA systems using GMPSCs also remove optical interference with intensity varying by blocks with a length of q. The proposed codes, referred to as p-chip codes in general and chip-pair codes in particular for the case of p=2, have the property of removing interference light with an intensity varying by shorter blocks with a length of p without requiring additional equipment. The present paper also investigates the algebraic properties and applications of the proposed codes.

Network Slicing (NS) is recognized as a key technology for the 5G network in providing tailored network services towards various types of verticals over a shared physical infrastructure. It offers the flexibility of on-demand provisioning of diverse services based on tenants' requirements in a dynamic environment. In this work, we focus on two important issues related to 5G Core slices: the deployment and the reconfiguration of 5G Core NSs. Firstly, for slice deployment, balancing the workloads of the underlying network is beneficial in mitigating resource fragmentation for accommodating the future unknown network slice requests. In this vein, we formulate a load-balancing oriented 5G Core NS deployment problem through an Integer Linear Program (ILP) formulation. Further, for slice reconfiguration, we propose a reactive strategy to accommodate a rejected NS request by reorganizing the already-deployed NSs. Typically, the NS deployment algorithm is reutilized with slacked physical resources to find out the congested part of the network, due to which the NS is rejected. Then, these congested physical nodes and links are reconfigured by migrating virtual network functions and virtual links, to re-balance the utilization of the whole physical network. To evaluate the performance of deployment and reconfiguration algorithms we proposed, extensive simulations have been conducted. The results show that our deployment algorithm performs better in resource balancing, hence achieves higher acceptance ratio by comparing to existing works. Moreover, our reconfiguration algorithm improves resource utilization by accommodating more NSs in a dynamic environment.

A properly designed stopping criterion for iterative decoding algorithms can save a number of iterations and lead to a considerable reduction of system latency. The symbol flipping decoding algorithms based on prediction (SFDP) have been proposed recently for efficient decoding of non-binary low-density parity-check (LDPC) codes. To detect the decoding frames with slow convergence or even non-convergence, we track the number of oscillations on the value of objective function during the iterations. Based on this tracking number, we design a simple stopping criterion for the SFDP algorithms. Simulation results show that the proposed stopping criterion can significantly reduce the number of iterations at low signal-to-noise ratio regions with slight error performance degradation.

A construction method of self-orthogonal and self-dual quasi-cyclic codes is shown which relies on factorization of modulus polynomials for cyclicity in this study. The smaller-size generator polynomial matrices are used instead of the generator matrices as linear codes. An algorithm based on Chinese remainder theorem finds the generator polynomial matrix on the original modulus from the ones constructed on each factor. This method enables us to efficiently construct and search these codes when factoring modulus polynomials into reciprocal polynomials.