IEICE TRANSACTIONS on Fundamentals
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits
Summary :
Optical logic circuits based on integrated nanophotonics attract significant interest due to their ultra-high-speed operation. However, the power dissipation of conventional optical logic circuits is exponential to the number of inputs of target logic functions. This paper proposes a synthesis method reducing power dissipation to a polynomial order of the number of inputs while exploiting the high-speed nature. Our method divides the target logic function into multiple sub-functions with Optical-to-Electrical (OE) converters. Each sub-function has a smaller number of inputs than that of the original function, which enables to exponentially reduce the power dissipated by an optical logic circuit representing the sub-function. The proposed synthesis method can mitigate the OE converter delay overhead by parallelizing sub-functions. We apply the proposed synthesis method to the ISCAS'85 benchmark circuits. The power consumption of the conventional circuits based on the Binary Decision Diagram (BDD) is at least three orders of magnitude larger than that of the optical logic circuits synthesized by the proposed method. The proposed method reduces the power consumption to about 100mW. The delay of almost all the circuits synthesized by the proposed method is kept less than four times the delay of the conventional BDD-based circuit.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E104-A No.11 pp.1546-1554
- Publication Date
- 2021/11/01
- Publicized
- 2021/05/18
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.2020KEP0018
- Type of Manuscript
- Special Section PAPER (Special Section on Circuits and Systems)
- Category
Authors
Ryosuke MATSUO
Kyoto University
Jun SHIOMI
Kyoto University
Tohru ISHIHARA
Nagoya University
Hidetoshi ONODERA
Kyoto University
Akihiko SHINYA
NTT Nanophotonics Center,NTT Basic Research Laboratories
Masaya NOTOMI
NTT Nanophotonics Center,NTT Basic Research Laboratories
Keyword
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Ryosuke MATSUO, Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, Akihiko SHINYA, Masaya NOTOMI, "A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E104-A, no. 11, pp. 1546-1554, November 2021, doi: 10.1587/transfun.2020KEP0018.
Abstract: Optical logic circuits based on integrated nanophotonics attract significant interest due to their ultra-high-speed operation. However, the power dissipation of conventional optical logic circuits is exponential to the number of inputs of target logic functions. This paper proposes a synthesis method reducing power dissipation to a polynomial order of the number of inputs while exploiting the high-speed nature. Our method divides the target logic function into multiple sub-functions with Optical-to-Electrical (OE) converters. Each sub-function has a smaller number of inputs than that of the original function, which enables to exponentially reduce the power dissipated by an optical logic circuit representing the sub-function. The proposed synthesis method can mitigate the OE converter delay overhead by parallelizing sub-functions. We apply the proposed synthesis method to the ISCAS'85 benchmark circuits. The power consumption of the conventional circuits based on the Binary Decision Diagram (BDD) is at least three orders of magnitude larger than that of the optical logic circuits synthesized by the proposed method. The proposed method reduces the power consumption to about 100mW. The delay of almost all the circuits synthesized by the proposed method is kept less than four times the delay of the conventional BDD-based circuit.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2020KEP0018/_p
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@ARTICLE{e104-a_11_1546,
author={Ryosuke MATSUO, Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, Akihiko SHINYA, Masaya NOTOMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits},
year={2021},
volume={E104-A},
number={11},
pages={1546-1554},
abstract={Optical logic circuits based on integrated nanophotonics attract significant interest due to their ultra-high-speed operation. However, the power dissipation of conventional optical logic circuits is exponential to the number of inputs of target logic functions. This paper proposes a synthesis method reducing power dissipation to a polynomial order of the number of inputs while exploiting the high-speed nature. Our method divides the target logic function into multiple sub-functions with Optical-to-Electrical (OE) converters. Each sub-function has a smaller number of inputs than that of the original function, which enables to exponentially reduce the power dissipated by an optical logic circuit representing the sub-function. The proposed synthesis method can mitigate the OE converter delay overhead by parallelizing sub-functions. We apply the proposed synthesis method to the ISCAS'85 benchmark circuits. The power consumption of the conventional circuits based on the Binary Decision Diagram (BDD) is at least three orders of magnitude larger than that of the optical logic circuits synthesized by the proposed method. The proposed method reduces the power consumption to about 100mW. The delay of almost all the circuits synthesized by the proposed method is kept less than four times the delay of the conventional BDD-based circuit.},
keywords={},
doi={10.1587/transfun.2020KEP0018},
ISSN={1745-1337},
month={November},}
Copy
TY - JOUR
TI - A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1546
EP - 1554
AU - Ryosuke MATSUO
AU - Jun SHIOMI
AU - Tohru ISHIHARA
AU - Hidetoshi ONODERA
AU - Akihiko SHINYA
AU - Masaya NOTOMI
PY - 2021
DO - 10.1587/transfun.2020KEP0018
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E104-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2021
AB - Optical logic circuits based on integrated nanophotonics attract significant interest due to their ultra-high-speed operation. However, the power dissipation of conventional optical logic circuits is exponential to the number of inputs of target logic functions. This paper proposes a synthesis method reducing power dissipation to a polynomial order of the number of inputs while exploiting the high-speed nature. Our method divides the target logic function into multiple sub-functions with Optical-to-Electrical (OE) converters. Each sub-function has a smaller number of inputs than that of the original function, which enables to exponentially reduce the power dissipated by an optical logic circuit representing the sub-function. The proposed synthesis method can mitigate the OE converter delay overhead by parallelizing sub-functions. We apply the proposed synthesis method to the ISCAS'85 benchmark circuits. The power consumption of the conventional circuits based on the Binary Decision Diagram (BDD) is at least three orders of magnitude larger than that of the optical logic circuits synthesized by the proposed method. The proposed method reduces the power consumption to about 100mW. The delay of almost all the circuits synthesized by the proposed method is kept less than four times the delay of the conventional BDD-based circuit.
ER -
English
