Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection

Takehiro KITAMURA; Mahfuzul ISLAM; Takashi HISAKADO; Osami WADA

doi:10.1587/transfun.2021KEP0007

Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection

Takehiro KITAMURA, Mahfuzul ISLAM, Takashi HISAKADO, Osami WADA

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High-speed flash ADCs are useful in high-speed applications such as communication receivers. Due to offset voltage variation in the sub-micron processes, the power consumption and the area increase significantly to suppress variation. As an alternative to suppressing the variation, we have developed a flash ADC architecture that selects the comparators based on offset voltage ranking for reference generation. Specifically, with the order statistics as a basis, our method selects the minimum number of comparators to obtain equally spaced reference values. Because the proposed ADC utilizes offset voltages as references, no resistor ladder is required. We also developed a time-domain sorting mechanism for the offset voltages to achieve on-chip comparator selection. We first perform a detailed analysis of the order statistics based selection method and then design a 4-bit ADC in a commercial 65-nm process and perform transistor-level simulation. When using 127 comparators, INLs of 20 virtual chips are in the range of -0.34LSB/+0.29LSB to -0.83LSB/+0.74LSB, and DNLs are in the range of -0.33LSB/+0.24LSB to -0.77LSB/+1.18LSB at 1-GS/s operation. Our ADC achieves the SNDR of 20.9dB at Nyquist-frequency input and the power consumption of 0.84mW.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E105-A No.11 pp.1450-1457

Publication Date: 2022/11/01

Publicized: 2022/05/13

Online ISSN: 1745-1337

DOI: 10.1587/transfun.2021KEP0007

Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems)

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Authors

Takehiro KITAMURA
  Kyoto University
Mahfuzul ISLAM
  Kyoto University
Takashi HISAKADO
  Kyoto University
Osami WADA
  Kyoto University

Keyword

flash ADC, offset voltage, order statistics, on-chip calibration

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Takehiro KITAMURA, Mahfuzul ISLAM, Takashi HISAKADO, Osami WADA, "Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection" in IEICE TRANSACTIONS on Fundamentals, vol. E105-A, no. 11, pp. 1450-1457, November 2022, doi: 10.1587/transfun.2021KEP0007.
Abstract: High-speed flash ADCs are useful in high-speed applications such as communication receivers. Due to offset voltage variation in the sub-micron processes, the power consumption and the area increase significantly to suppress variation. As an alternative to suppressing the variation, we have developed a flash ADC architecture that selects the comparators based on offset voltage ranking for reference generation. Specifically, with the order statistics as a basis, our method selects the minimum number of comparators to obtain equally spaced reference values. Because the proposed ADC utilizes offset voltages as references, no resistor ladder is required. We also developed a time-domain sorting mechanism for the offset voltages to achieve on-chip comparator selection. We first perform a detailed analysis of the order statistics based selection method and then design a 4-bit ADC in a commercial 65-nm process and perform transistor-level simulation. When using 127 comparators, INLs of 20 virtual chips are in the range of -0.34LSB/+0.29LSB to -0.83LSB/+0.74LSB, and DNLs are in the range of -0.33LSB/+0.24LSB to -0.77LSB/+1.18LSB at 1-GS/s operation. Our ADC achieves the SNDR of 20.9dB at Nyquist-frequency input and the power consumption of 0.84mW.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021KEP0007/_p

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@ARTICLE{e105-a_11_1450,
author={Takehiro KITAMURA, Mahfuzul ISLAM, Takashi HISAKADO, Osami WADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection},
year={2022},
volume={E105-A},
number={11},
pages={1450-1457},
abstract={High-speed flash ADCs are useful in high-speed applications such as communication receivers. Due to offset voltage variation in the sub-micron processes, the power consumption and the area increase significantly to suppress variation. As an alternative to suppressing the variation, we have developed a flash ADC architecture that selects the comparators based on offset voltage ranking for reference generation. Specifically, with the order statistics as a basis, our method selects the minimum number of comparators to obtain equally spaced reference values. Because the proposed ADC utilizes offset voltages as references, no resistor ladder is required. We also developed a time-domain sorting mechanism for the offset voltages to achieve on-chip comparator selection. We first perform a detailed analysis of the order statistics based selection method and then design a 4-bit ADC in a commercial 65-nm process and perform transistor-level simulation. When using 127 comparators, INLs of 20 virtual chips are in the range of -0.34LSB/+0.29LSB to -0.83LSB/+0.74LSB, and DNLs are in the range of -0.33LSB/+0.24LSB to -0.77LSB/+1.18LSB at 1-GS/s operation. Our ADC achieves the SNDR of 20.9dB at Nyquist-frequency input and the power consumption of 0.84mW.},
keywords={},
doi={10.1587/transfun.2021KEP0007},
ISSN={1745-1337},
month={November},}

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TY - JOUR
TI - Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1450
EP - 1457
AU - Takehiro KITAMURA
AU - Mahfuzul ISLAM
AU - Takashi HISAKADO
AU - Osami WADA
PY - 2022
DO - 10.1587/transfun.2021KEP0007
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2022
AB - High-speed flash ADCs are useful in high-speed applications such as communication receivers. Due to offset voltage variation in the sub-micron processes, the power consumption and the area increase significantly to suppress variation. As an alternative to suppressing the variation, we have developed a flash ADC architecture that selects the comparators based on offset voltage ranking for reference generation. Specifically, with the order statistics as a basis, our method selects the minimum number of comparators to obtain equally spaced reference values. Because the proposed ADC utilizes offset voltages as references, no resistor ladder is required. We also developed a time-domain sorting mechanism for the offset voltages to achieve on-chip comparator selection. We first perform a detailed analysis of the order statistics based selection method and then design a 4-bit ADC in a commercial 65-nm process and perform transistor-level simulation. When using 127 comparators, INLs of 20 virtual chips are in the range of -0.34LSB/+0.29LSB to -0.83LSB/+0.74LSB, and DNLs are in the range of -0.33LSB/+0.24LSB to -0.77LSB/+1.18LSB at 1-GS/s operation. Our ADC achieves the SNDR of 20.9dB at Nyquist-frequency input and the power consumption of 0.84mW.
ER -