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Open Access
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling

Yutaka MASUDA, Jun NAGAYAMA, TaiYu CHENG, Tohru ISHIHARA, Yoichi MOMIYAMA, Masanori HASHIMOTO

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Summary :

This work proposes a design methodology that saves the power dissipation under voltage over-scaling (VOS) operation. The key idea of the proposed design methodology is to combine critical path isolation (CPI) and bit-width scaling (BWS) under the constraint of computational quality, e.g., Peak Signal-to-Noise Ratio (PSNR) in the image processing domain. Conventional CPI inherently cannot reduce the delay of intrinsic critical paths (CPs), which may significantly restrict the power saving effect. On the other hand, the proposed methodology tries to reduce both intrinsic and non-intrinsic CPs. Therefore, our design dramatically reduces the supply voltage and power dissipation while satisfying the quality constraint. Moreover, for reducing co-design exploration space, the proposed methodology utilizes the exclusiveness of the paths targeted by CPI and BWS, where CPI aims at reducing the minimum supply voltage of non-intrinsic CP, and BWS focuses on intrinsic CPs in arithmetic units. From this key exclusiveness, the proposed design splits the simultaneous optimization problem into three sub-problems; (1) the determination of bit-width reduction, (2) the timing optimization for non-intrinsic CPs, and (3) investigating the minimum supply voltage of the BWS and CPI-applied circuit under quality constraint, for reducing power dissipation. Thanks to the problem splitting, the proposed methodology can efficiently find quality-constrained minimum-power design. Evaluation results show that CPI and BWS are highly compatible, and they significantly enhance the efficacy of VOS. In a case study of a GPGPU processor, the proposed design saves the power dissipation by 42.7% with an image processing workload and by 51.2% with a neural network inference workload.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E105-A No.3 pp.509-517
Publication Date
2022/03/01
Publicized
2021/08/31
Online ISSN
1745-1337
DOI
10.1587/transfun.2021VLP0002
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category

Authors

Yutaka MASUDA
  Nagoya University
Jun NAGAYAMA
  the Socionext Inc.
TaiYu CHENG
  Osaka University
Tohru ISHIHARA
  Nagoya University
Yoichi MOMIYAMA
  the Socionext Inc.
Masanori HASHIMOTO
  Osaka University

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