IEICE TRANSACTIONS on Fundamentals
Identification and Application of Invariant Critical Paths under NBTI Degradation
Summary :
As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) are known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and propose a two-stage path extraction algorithm to identify the invariant critical paths (ICPs) in the processor. Utilizing these paths, we also propose an optimization technique for the replacement of internal node control logic that mitigates the NBTI degradation in the design. Through numerical experiment on two processor designs, we achieved nearly 300x reduction in the sheer number of paths on both designs. Utilizing the extracted ICPs, we achieved 96x-197x speedup without loss in mitigation gain.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.12 pp.2797-2806
- Publication Date
- 2017/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E100.A.2797
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Song BIAN
Kyoto University
Shumpei MORITA
Kyoto University
Michihiro SHINTANI
Kyoto University
Hiromitsu AWANO
Kyoto University
Masayuki HIROMOTO
Kyoto University
Takashi SATO
Kyoto University
Keyword
Latest Issue
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Song BIAN, Shumpei MORITA, Michihiro SHINTANI, Hiromitsu AWANO, Masayuki HIROMOTO, Takashi SATO, "Identification and Application of Invariant Critical Paths under NBTI Degradation" in IEICE TRANSACTIONS on Fundamentals,
vol. E100-A, no. 12, pp. 2797-2806, December 2017, doi: 10.1587/transfun.E100.A.2797.
Abstract: As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) are known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and propose a two-stage path extraction algorithm to identify the invariant critical paths (ICPs) in the processor. Utilizing these paths, we also propose an optimization technique for the replacement of internal node control logic that mitigates the NBTI degradation in the design. Through numerical experiment on two processor designs, we achieved nearly 300x reduction in the sheer number of paths on both designs. Utilizing the extracted ICPs, we achieved 96x-197x speedup without loss in mitigation gain.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.2797/_p
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@ARTICLE{e100-a_12_2797,
author={Song BIAN, Shumpei MORITA, Michihiro SHINTANI, Hiromitsu AWANO, Masayuki HIROMOTO, Takashi SATO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Identification and Application of Invariant Critical Paths under NBTI Degradation},
year={2017},
volume={E100-A},
number={12},
pages={2797-2806},
abstract={As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) are known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and propose a two-stage path extraction algorithm to identify the invariant critical paths (ICPs) in the processor. Utilizing these paths, we also propose an optimization technique for the replacement of internal node control logic that mitigates the NBTI degradation in the design. Through numerical experiment on two processor designs, we achieved nearly 300x reduction in the sheer number of paths on both designs. Utilizing the extracted ICPs, we achieved 96x-197x speedup without loss in mitigation gain.},
keywords={},
doi={10.1587/transfun.E100.A.2797},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Identification and Application of Invariant Critical Paths under NBTI Degradation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2797
EP - 2806
AU - Song BIAN
AU - Shumpei MORITA
AU - Michihiro SHINTANI
AU - Hiromitsu AWANO
AU - Masayuki HIROMOTO
AU - Takashi SATO
PY - 2017
DO - 10.1587/transfun.E100.A.2797
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2017
AB - As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) are known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and propose a two-stage path extraction algorithm to identify the invariant critical paths (ICPs) in the processor. Utilizing these paths, we also propose an optimization technique for the replacement of internal node control logic that mitigates the NBTI degradation in the design. Through numerical experiment on two processor designs, we achieved nearly 300x reduction in the sheer number of paths on both designs. Utilizing the extracted ICPs, we achieved 96x-197x speedup without loss in mitigation gain.
ER -
English
