IEICE TRANSACTIONS on Fundamentals
A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element
Summary :
To deal with the reliability issue caused by soft errors, this paper proposed a low power soft error hardened latch (SHC) design using a novel Schmitt-Trigger-based C-element for reliable low power applications. Unlike state-of-the-art soft error tolerant latches that are usually based on hardware redundancy with large area overhead and high power consumption, the proposed SHC latch is implemented through double-sampling and node-checking using a novel Schmitt-Trigger-based C-element, which can help to reduce the area overhead and the corresponding power consumption as well. The evaluation results show that the total number of transistors of the proposed SHC latch is only increased by 2 when compared to the conventional unhardened C2MOS latch, while up to 20.35% and 82.96% power reduction can be achieved when compared to the conventional unhardened C2MOS latch and the existing soft error tolerant HiPeR design, respectively.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.7 pp.1025-1034
- Publication Date
- 2018/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E101.A.1025
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Saki TAJIMA
Waseda University
Nozomu TOGAWA
Waseda University
Masao YANAGISAWA
Waseda University
Youhua SHI
Waseda University
Keyword
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Saki TAJIMA, Nozomu TOGAWA, Masao YANAGISAWA, Youhua SHI, "A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 7, pp. 1025-1034, July 2018, doi: 10.1587/transfun.E101.A.1025.
Abstract: To deal with the reliability issue caused by soft errors, this paper proposed a low power soft error hardened latch (SHC) design using a novel Schmitt-Trigger-based C-element for reliable low power applications. Unlike state-of-the-art soft error tolerant latches that are usually based on hardware redundancy with large area overhead and high power consumption, the proposed SHC latch is implemented through double-sampling and node-checking using a novel Schmitt-Trigger-based C-element, which can help to reduce the area overhead and the corresponding power consumption as well. The evaluation results show that the total number of transistors of the proposed SHC latch is only increased by 2 when compared to the conventional unhardened C2MOS latch, while up to 20.35% and 82.96% power reduction can be achieved when compared to the conventional unhardened C2MOS latch and the existing soft error tolerant HiPeR design, respectively.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.1025/_p
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@ARTICLE{e101-a_7_1025,
author={Saki TAJIMA, Nozomu TOGAWA, Masao YANAGISAWA, Youhua SHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element},
year={2018},
volume={E101-A},
number={7},
pages={1025-1034},
abstract={To deal with the reliability issue caused by soft errors, this paper proposed a low power soft error hardened latch (SHC) design using a novel Schmitt-Trigger-based C-element for reliable low power applications. Unlike state-of-the-art soft error tolerant latches that are usually based on hardware redundancy with large area overhead and high power consumption, the proposed SHC latch is implemented through double-sampling and node-checking using a novel Schmitt-Trigger-based C-element, which can help to reduce the area overhead and the corresponding power consumption as well. The evaluation results show that the total number of transistors of the proposed SHC latch is only increased by 2 when compared to the conventional unhardened C2MOS latch, while up to 20.35% and 82.96% power reduction can be achieved when compared to the conventional unhardened C2MOS latch and the existing soft error tolerant HiPeR design, respectively.},
keywords={},
doi={10.1587/transfun.E101.A.1025},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1025
EP - 1034
AU - Saki TAJIMA
AU - Nozomu TOGAWA
AU - Masao YANAGISAWA
AU - Youhua SHI
PY - 2018
DO - 10.1587/transfun.E101.A.1025
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2018
AB - To deal with the reliability issue caused by soft errors, this paper proposed a low power soft error hardened latch (SHC) design using a novel Schmitt-Trigger-based C-element for reliable low power applications. Unlike state-of-the-art soft error tolerant latches that are usually based on hardware redundancy with large area overhead and high power consumption, the proposed SHC latch is implemented through double-sampling and node-checking using a novel Schmitt-Trigger-based C-element, which can help to reduce the area overhead and the corresponding power consumption as well. The evaluation results show that the total number of transistors of the proposed SHC latch is only increased by 2 when compared to the conventional unhardened C2MOS latch, while up to 20.35% and 82.96% power reduction can be achieved when compared to the conventional unhardened C2MOS latch and the existing soft error tolerant HiPeR design, respectively.
ER -
English
