IEICE TRANSACTIONS on Fundamentals
Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis
Summary :
This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.12 pp.2222-2230
- Publication Date
- 2018/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E101.A.2222
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Shinichi NISHIZAWA
Saitama University
Hidetoshi ONODERA
Kyoto University
Keyword
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Shinichi NISHIZAWA, Hidetoshi ONODERA, "Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 12, pp. 2222-2230, December 2018, doi: 10.1587/transfun.E101.A.2222.
Abstract: This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.2222/_p
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@ARTICLE{e101-a_12_2222,
author={Shinichi NISHIZAWA, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis},
year={2018},
volume={E101-A},
number={12},
pages={2222-2230},
abstract={This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.},
keywords={},
doi={10.1587/transfun.E101.A.2222},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2222
EP - 2230
AU - Shinichi NISHIZAWA
AU - Hidetoshi ONODERA
PY - 2018
DO - 10.1587/transfun.E101.A.2222
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2018
AB - This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.
ER -
English
