IEICE TRANSACTIONS on Fundamentals
Passage of Faulty Nodes: A Novel Approach for Fault-Tolerant Routing on NoCs
Summary :
This paper addresses the problem of developing an efficient fault-tolerant routing method for 2D mesh Network-on-Chips (NoCs) to realize dependable and high performance many core systems. Existing fault-tolerant routing methods have two critical problems of high communication latency and low node utilization. Unlike almost all existing methods where packets always detour faulty nodes, we propose a novel and unique approach that packets can pass through faulty nodes. For this approach, we enhance the common NoC architecture by adding switches and links around each node and propose a fault-tolerant routing method with no virtual channels based on the well-known simple XY routing method. Simulation results show that the proposed method reduces average communication latency by about 97.1% compared with the existing method, without sacrificing fault-free nodes.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.12 pp.1702-1710
- Publication Date
- 2019/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E102.A.1702
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Yota KUROKAWA
Yamaguchi University
Masaru FUKUSHI
Yamaguchi University
Keyword
Latest Issue
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Yota KUROKAWA, Masaru FUKUSHI, "Passage of Faulty Nodes: A Novel Approach for Fault-Tolerant Routing on NoCs" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 12, pp. 1702-1710, December 2019, doi: 10.1587/transfun.E102.A.1702.
Abstract: This paper addresses the problem of developing an efficient fault-tolerant routing method for 2D mesh Network-on-Chips (NoCs) to realize dependable and high performance many core systems. Existing fault-tolerant routing methods have two critical problems of high communication latency and low node utilization. Unlike almost all existing methods where packets always detour faulty nodes, we propose a novel and unique approach that packets can pass through faulty nodes. For this approach, we enhance the common NoC architecture by adding switches and links around each node and propose a fault-tolerant routing method with no virtual channels based on the well-known simple XY routing method. Simulation results show that the proposed method reduces average communication latency by about 97.1% compared with the existing method, without sacrificing fault-free nodes.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.1702/_p
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@ARTICLE{e102-a_12_1702,
author={Yota KUROKAWA, Masaru FUKUSHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Passage of Faulty Nodes: A Novel Approach for Fault-Tolerant Routing on NoCs},
year={2019},
volume={E102-A},
number={12},
pages={1702-1710},
abstract={This paper addresses the problem of developing an efficient fault-tolerant routing method for 2D mesh Network-on-Chips (NoCs) to realize dependable and high performance many core systems. Existing fault-tolerant routing methods have two critical problems of high communication latency and low node utilization. Unlike almost all existing methods where packets always detour faulty nodes, we propose a novel and unique approach that packets can pass through faulty nodes. For this approach, we enhance the common NoC architecture by adding switches and links around each node and propose a fault-tolerant routing method with no virtual channels based on the well-known simple XY routing method. Simulation results show that the proposed method reduces average communication latency by about 97.1% compared with the existing method, without sacrificing fault-free nodes.},
keywords={},
doi={10.1587/transfun.E102.A.1702},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Passage of Faulty Nodes: A Novel Approach for Fault-Tolerant Routing on NoCs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1702
EP - 1710
AU - Yota KUROKAWA
AU - Masaru FUKUSHI
PY - 2019
DO - 10.1587/transfun.E102.A.1702
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2019
AB - This paper addresses the problem of developing an efficient fault-tolerant routing method for 2D mesh Network-on-Chips (NoCs) to realize dependable and high performance many core systems. Existing fault-tolerant routing methods have two critical problems of high communication latency and low node utilization. Unlike almost all existing methods where packets always detour faulty nodes, we propose a novel and unique approach that packets can pass through faulty nodes. For this approach, we enhance the common NoC architecture by adding switches and links around each node and propose a fault-tolerant routing method with no virtual channels based on the well-known simple XY routing method. Simulation results show that the proposed method reduces average communication latency by about 97.1% compared with the existing method, without sacrificing fault-free nodes.
ER -
English
