IEICE TRANSACTIONS on Fundamentals
Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution
Summary :
Correctly understanding microarchitectural bottlenecks is important to optimize performance and energy of OoO (Out-of-Order) processors. Although CPI (Cycles Per Instruction) stack has been utilized for this purpose, it stacks architectural events heuristically by counting how many times the events occur, and the order of stacking affects the result, which may be misleading. It is because CPI stack does not consider the execution path of dynamic instructions. Critical path analysis (CPA) is a well-known method to identify the critical execution path of dynamic instruction execution on OoO processors. The critical path consists of the sequence of events that determines the execution time of a program on a certain processor. We develop a novel representation of CPCI stack (Cycles Per Critical Instruction stack), which is CPI stack based on CPA. The main challenge in constructing CPCI stack is how to analyze a large number of paths because CPA often results in numerous critical paths. In this paper, we show that there are more than ten to the tenth power critical paths in the execution of only one thousand instructions in 35 benchmarks out of 48 from SPEC CPU2006. Then, we propose a statistical method to analyze all the critical paths and show a case study using the benchmarks.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.6 pp.758-766
- Publication Date
- 2019/06/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E102.A.758
- Type of Manuscript
- Special Section PAPER (Special Section on Circuits and Systems)
- Category
Authors
Teruo TANIMOTO
Kyushu University
Takatsugu ONO
Kyushu University
Koji INOUE
Kyushu University
Keyword
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Teruo TANIMOTO, Takatsugu ONO, Koji INOUE, "Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 6, pp. 758-766, June 2019, doi: 10.1587/transfun.E102.A.758.
Abstract: Correctly understanding microarchitectural bottlenecks is important to optimize performance and energy of OoO (Out-of-Order) processors. Although CPI (Cycles Per Instruction) stack has been utilized for this purpose, it stacks architectural events heuristically by counting how many times the events occur, and the order of stacking affects the result, which may be misleading. It is because CPI stack does not consider the execution path of dynamic instructions. Critical path analysis (CPA) is a well-known method to identify the critical execution path of dynamic instruction execution on OoO processors. The critical path consists of the sequence of events that determines the execution time of a program on a certain processor. We develop a novel representation of CPCI stack (Cycles Per Critical Instruction stack), which is CPI stack based on CPA. The main challenge in constructing CPCI stack is how to analyze a large number of paths because CPA often results in numerous critical paths. In this paper, we show that there are more than ten to the tenth power critical paths in the execution of only one thousand instructions in 35 benchmarks out of 48 from SPEC CPU2006. Then, we propose a statistical method to analyze all the critical paths and show a case study using the benchmarks.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.758/_p
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@ARTICLE{e102-a_6_758,
author={Teruo TANIMOTO, Takatsugu ONO, Koji INOUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution},
year={2019},
volume={E102-A},
number={6},
pages={758-766},
abstract={Correctly understanding microarchitectural bottlenecks is important to optimize performance and energy of OoO (Out-of-Order) processors. Although CPI (Cycles Per Instruction) stack has been utilized for this purpose, it stacks architectural events heuristically by counting how many times the events occur, and the order of stacking affects the result, which may be misleading. It is because CPI stack does not consider the execution path of dynamic instructions. Critical path analysis (CPA) is a well-known method to identify the critical execution path of dynamic instruction execution on OoO processors. The critical path consists of the sequence of events that determines the execution time of a program on a certain processor. We develop a novel representation of CPCI stack (Cycles Per Critical Instruction stack), which is CPI stack based on CPA. The main challenge in constructing CPCI stack is how to analyze a large number of paths because CPA often results in numerous critical paths. In this paper, we show that there are more than ten to the tenth power critical paths in the execution of only one thousand instructions in 35 benchmarks out of 48 from SPEC CPU2006. Then, we propose a statistical method to analyze all the critical paths and show a case study using the benchmarks.},
keywords={},
doi={10.1587/transfun.E102.A.758},
ISSN={1745-1337},
month={June},}
Copy
TY - JOUR
TI - Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 758
EP - 766
AU - Teruo TANIMOTO
AU - Takatsugu ONO
AU - Koji INOUE
PY - 2019
DO - 10.1587/transfun.E102.A.758
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2019
AB - Correctly understanding microarchitectural bottlenecks is important to optimize performance and energy of OoO (Out-of-Order) processors. Although CPI (Cycles Per Instruction) stack has been utilized for this purpose, it stacks architectural events heuristically by counting how many times the events occur, and the order of stacking affects the result, which may be misleading. It is because CPI stack does not consider the execution path of dynamic instructions. Critical path analysis (CPA) is a well-known method to identify the critical execution path of dynamic instruction execution on OoO processors. The critical path consists of the sequence of events that determines the execution time of a program on a certain processor. We develop a novel representation of CPCI stack (Cycles Per Critical Instruction stack), which is CPI stack based on CPA. The main challenge in constructing CPCI stack is how to analyze a large number of paths because CPA often results in numerous critical paths. In this paper, we show that there are more than ten to the tenth power critical paths in the execution of only one thousand instructions in 35 benchmarks out of 48 from SPEC CPU2006. Then, we propose a statistical method to analyze all the critical paths and show a case study using the benchmarks.
ER -
English
