IEICE TRANSACTIONS on Fundamentals
Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning
Summary :
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates and wires in fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into clock trees before the fabrication and adjusts the delays of the PDEs to recover the timing violation after the fabrication, is promising to improve the yield. Although post-silicon delay tuning improves the yield, it increases circuit area and power consumption since the PDEs are inserted. In this paper, a PDE structure is taken into consideration to reduce the circuit area and the power consumption. Moreover, a delay selection algorithm, and a clustering method, in which some PDEs are merged into a PDE and the PDE is inserted for multiple registers, are proposed to reduce the circuit area and the power consumption. In computational experiments, the proposed method reduced the circuit area and the power consumption in comparison with an existing method.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.7 pp.894-903
- Publication Date
- 2019/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E102.A.894
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Kota MUROI
the University of Aizu
Hayato MASHIKO
the University of Aizu
Yukihide KOHIRA
the University of Aizu
Keyword
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Kota MUROI, Hayato MASHIKO, Yukihide KOHIRA, "Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 7, pp. 894-903, July 2019, doi: 10.1587/transfun.E102.A.894.
Abstract: Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates and wires in fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into clock trees before the fabrication and adjusts the delays of the PDEs to recover the timing violation after the fabrication, is promising to improve the yield. Although post-silicon delay tuning improves the yield, it increases circuit area and power consumption since the PDEs are inserted. In this paper, a PDE structure is taken into consideration to reduce the circuit area and the power consumption. Moreover, a delay selection algorithm, and a clustering method, in which some PDEs are merged into a PDE and the PDE is inserted for multiple registers, are proposed to reduce the circuit area and the power consumption. In computational experiments, the proposed method reduced the circuit area and the power consumption in comparison with an existing method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.894/_p
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@ARTICLE{e102-a_7_894,
author={Kota MUROI, Hayato MASHIKO, Yukihide KOHIRA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning},
year={2019},
volume={E102-A},
number={7},
pages={894-903},
abstract={Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates and wires in fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into clock trees before the fabrication and adjusts the delays of the PDEs to recover the timing violation after the fabrication, is promising to improve the yield. Although post-silicon delay tuning improves the yield, it increases circuit area and power consumption since the PDEs are inserted. In this paper, a PDE structure is taken into consideration to reduce the circuit area and the power consumption. Moreover, a delay selection algorithm, and a clustering method, in which some PDEs are merged into a PDE and the PDE is inserted for multiple registers, are proposed to reduce the circuit area and the power consumption. In computational experiments, the proposed method reduced the circuit area and the power consumption in comparison with an existing method.},
keywords={},
doi={10.1587/transfun.E102.A.894},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 894
EP - 903
AU - Kota MUROI
AU - Hayato MASHIKO
AU - Yukihide KOHIRA
PY - 2019
DO - 10.1587/transfun.E102.A.894
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2019
AB - Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates and wires in fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into clock trees before the fabrication and adjusts the delays of the PDEs to recover the timing violation after the fabrication, is promising to improve the yield. Although post-silicon delay tuning improves the yield, it increases circuit area and power consumption since the PDEs are inserted. In this paper, a PDE structure is taken into consideration to reduce the circuit area and the power consumption. Moreover, a delay selection algorithm, and a clustering method, in which some PDEs are merged into a PDE and the PDE is inserted for multiple registers, are proposed to reduce the circuit area and the power consumption. In computational experiments, the proposed method reduced the circuit area and the power consumption in comparison with an existing method.
ER -
English
