IEICE TRANSACTIONS on Fundamentals
Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework
Summary :
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, the circuit performance such as the clock period is expected to be improved by delay insertion. However, if the amount of inserted delays is too much, then the circuit is changed too much and the circuit performance might not be improved. In this paper, we propose an efficient delay insertion method that minimizes the amount of inserted delays in the clock period improvement in general-synchronous framework. In the proposed method, the amount of inserted delays is minimized by using an appropriate clock schedule and by inserting delays into appropriate places in the circuit. Experiments show that the proposed method can obtain optimum solutions in short time in many cases.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.4 pp.1106-1114
- Publication Date
- 2009/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.1106
- Type of Manuscript
- Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
- Category
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Yukihide KOHIRA, Shuhei TANI, Atsushi TAKAHASHI, "Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 4, pp. 1106-1114, April 2009, doi: 10.1587/transfun.E92.A.1106.
Abstract: In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, the circuit performance such as the clock period is expected to be improved by delay insertion. However, if the amount of inserted delays is too much, then the circuit is changed too much and the circuit performance might not be improved. In this paper, we propose an efficient delay insertion method that minimizes the amount of inserted delays in the clock period improvement in general-synchronous framework. In the proposed method, the amount of inserted delays is minimized by using an appropriate clock schedule and by inserting delays into appropriate places in the circuit. Experiments show that the proposed method can obtain optimum solutions in short time in many cases.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1106/_p
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@ARTICLE{e92-a_4_1106,
author={Yukihide KOHIRA, Shuhei TANI, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework},
year={2009},
volume={E92-A},
number={4},
pages={1106-1114},
abstract={In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, the circuit performance such as the clock period is expected to be improved by delay insertion. However, if the amount of inserted delays is too much, then the circuit is changed too much and the circuit performance might not be improved. In this paper, we propose an efficient delay insertion method that minimizes the amount of inserted delays in the clock period improvement in general-synchronous framework. In the proposed method, the amount of inserted delays is minimized by using an appropriate clock schedule and by inserting delays into appropriate places in the circuit. Experiments show that the proposed method can obtain optimum solutions in short time in many cases.},
keywords={},
doi={10.1587/transfun.E92.A.1106},
ISSN={1745-1337},
month={April},}
Copy
TY - JOUR
TI - Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1106
EP - 1114
AU - Yukihide KOHIRA
AU - Shuhei TANI
AU - Atsushi TAKAHASHI
PY - 2009
DO - 10.1587/transfun.E92.A.1106
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2009
AB - In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily simultaneously, the circuit performance such as the clock period is expected to be improved by delay insertion. However, if the amount of inserted delays is too much, then the circuit is changed too much and the circuit performance might not be improved. In this paper, we propose an efficient delay insertion method that minimizes the amount of inserted delays in the clock period improvement in general-synchronous framework. In the proposed method, the amount of inserted delays is minimized by using an appropriate clock schedule and by inserting delays into appropriate places in the circuit. Experiments show that the proposed method can obtain optimum solutions in short time in many cases.
ER -
English
