IEICE TRANSACTIONS on Fundamentals
Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping
Summary :
Checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. In the paper, we propose a checker synthesis method based on the finite input-memory automaton suitable for embedded RAM modules in FPGA. There are more than 1 Mbit memories in medium size FPGA's and such embedded memory cells have the capability to be used as the shift registers. The main idea is to construct a checker circuit using the finite input-memory automata and implement shift register chain by logic elements or embedded RAM modules. When using RAM module, the method does not consume any logic element for storing the value. Note that the shift register chain of input memory can be shared with different assertions and we can reduce the hardware resource significantly. We have checked the effectiveness of the proposed method using several assertions.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.6 pp.1454-1463
- Publication Date
- 2009/06/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.1454
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Chengjie ZANG, Shinji KIMURA, "Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 6, pp. 1454-1463, June 2009, doi: 10.1587/transfun.E92.A.1454.
Abstract: Checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. In the paper, we propose a checker synthesis method based on the finite input-memory automaton suitable for embedded RAM modules in FPGA. There are more than 1 Mbit memories in medium size FPGA's and such embedded memory cells have the capability to be used as the shift registers. The main idea is to construct a checker circuit using the finite input-memory automata and implement shift register chain by logic elements or embedded RAM modules. When using RAM module, the method does not consume any logic element for storing the value. Note that the shift register chain of input memory can be shared with different assertions and we can reduce the hardware resource significantly. We have checked the effectiveness of the proposed method using several assertions.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1454/_p
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@ARTICLE{e92-a_6_1454,
author={Chengjie ZANG, Shinji KIMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping},
year={2009},
volume={E92-A},
number={6},
pages={1454-1463},
abstract={Checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. In the paper, we propose a checker synthesis method based on the finite input-memory automaton suitable for embedded RAM modules in FPGA. There are more than 1 Mbit memories in medium size FPGA's and such embedded memory cells have the capability to be used as the shift registers. The main idea is to construct a checker circuit using the finite input-memory automata and implement shift register chain by logic elements or embedded RAM modules. When using RAM module, the method does not consume any logic element for storing the value. Note that the shift register chain of input memory can be shared with different assertions and we can reduce the hardware resource significantly. We have checked the effectiveness of the proposed method using several assertions.},
keywords={},
doi={10.1587/transfun.E92.A.1454},
ISSN={1745-1337},
month={June},}
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TY - JOUR
TI - Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1454
EP - 1463
AU - Chengjie ZANG
AU - Shinji KIMURA
PY - 2009
DO - 10.1587/transfun.E92.A.1454
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2009
AB - Checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. In the paper, we propose a checker synthesis method based on the finite input-memory automaton suitable for embedded RAM modules in FPGA. There are more than 1 Mbit memories in medium size FPGA's and such embedded memory cells have the capability to be used as the shift registers. The main idea is to construct a checker circuit using the finite input-memory automata and implement shift register chain by logic elements or embedded RAM modules. When using RAM module, the method does not consume any logic element for storing the value. Note that the shift register chain of input memory can be shared with different assertions and we can reduce the hardware resource significantly. We have checked the effectiveness of the proposed method using several assertions.
ER -
English
