In this paper, we propose a new system for controlling radiated sound directivity. The proposed system artificially induces a bending vibration on a planar diaphragm by vibrating it artificially using multiple vibrators. Because the bending vibration in this case is determined by not one but all of the accelerated vibrations, the vibration of the diaphragm can be controlled by modulating the accelerated vibration waveforms relatively for each frequency. As a consequence, the directivity of the radiated sound is also varied. To investigate the feasibility of this system, we constructed a prototype that has for a diaphragm a circular plate-one of the most typical shapes considered for discussing plate vibration-and three vibrators. The measurement data showed visually that with this system, surface vibration and sound directivity change depending on the phases of the accelerated vibrations.

We have introduced a new ultrasonic-based localization method that requires only one ultrasonic receiver to locate transmitters. In our previous reports [1],[2], we conducted several fundamental experiments, and proved the feasibility and accuracy of our system. However the performance in a more realistic environment has not yet been evaluated. In this paper, we have extended our localization system into a robot tracking system, and conducted experiments where the system tracked a moving robot. Localization was executed both by our proposed method and by the conventional TOA method. The experiment was repeated with different density of receivers. Thus we were able to compare the accuracy and the scalability between our proposed method and the conventional method. As a result 90-percentile of the position error was from 6.2 cm to 14.6 cm for the proposed method, from 4.0 cm to 6.1 cm for the conventional method. However our proposed method succeeded in calculating the position of the transmitter in 95% out of total attempts of localization with sparse receivers (4 receivers in about 5 m 5 m area), whereas the success rate was only 31% for the conventional method. From the result we concluded that although the proposed method is less accurate it can cover a wider area with sparse receivers than the conventional method. In addition to the dynamic tracking experiments, we also conducted some localization experiments where the robot stood still. This was because we wanted to investigate the reason why the localization accuracy degraded in the dynamic tracking. According to the result, the degradation of accuracy might be due to the systematic error in localization which is dependent on the geometric relationship between the transmitter and the receiver.

Distributed video coding (DVC) technology has been considered to be capable of reducing the processing complexity of the encoder immensely, while majority of the computational overheads are taken over by the decoder. In the common DVC framework, the pictures are decoded using the Wyner-Ziv encoded bit stream received from the encoder and the side information estimated using previously decoded information. As a result, accuracy of the side information estimation is very critical in improving the coding efficiency. In this paper we propose a novel side information refinement technique for DVC using multiple side information streams and sequential motion compensation with luminance and chrominance information involving iterative fusion of parallel information streams. In the bit plane wise coding architecture, previously decoded higher order bit planes are incrementally used to perform the motion estimation jointly in luminance and chrominance spaces to estimate multiple redundant bit streams for iterative fusion to produce more improved side information for subsequent bit planes. Simulation results show significant objective quality gain can be achieved at the same bit rate by utilizing the proposed refinement algorithms.

Cognitive radio (CR) is an adaptive spectrum sharing paradigm targeted to provide opportunistic spectrum access to secondary users for whom the frequency bands have not been licensed. The key tasks in a CR are to sense the spectral environment over a wide frequency band and allow unlicensed secondary users (CR users) to dynamically transmit/receive data over frequency bands unutilized by licensed primary users. Thus the CR transceiver should dynamically adapt its channel (frequency band) in response to the time-varying frequencies of wideband signal for seamless communication. In this paper, we present a low complexity reconfigurable filter architecture based on multi-band filtering and frequency masking techniques for dynamic channel adaptation in CR terminal. The proposed multi-standard architecture is capable of adapting to channels having different bandwidths corresponding to the channel spacing of time-varying channels. Design examples show that proposed architecture offers 12.2% power reduction and 26.5% average gate count reduction over conventional Per-Channel based architecture.

Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in manual routing. We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment. In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.

In an embedded system where a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: the number of sets, a line size, and an associativity. In this paper, we first propose two cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but decrease the number of cache hit/miss judgments dramatically. We further propose three more cache design space exploration algorithms: CRMF1, CRMF2, and CRMF3, based on our experimental observations. They can find an almost optimal cache configuration from the viewpoint of access time. By using our approach, the number of cache hit/miss judgments required for optimizing cache configurations is reduced to 1/10-1/50 compared to conventional approaches. As a result, our proposed approach totally runs an average of 3.2 times faster and a maximum of 5.3 times faster compared to the fastest approach proposed so far. Our proposed cache simulation approach achieves the world fastest cache design space exploration when optimizing total memory access time.

Checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. In the paper, we propose a checker synthesis method based on the finite input-memory automaton suitable for embedded RAM modules in FPGA. There are more than 1 Mbit memories in medium size FPGA's and such embedded memory cells have the capability to be used as the shift registers. The main idea is to construct a checker circuit using the finite input-memory automata and implement shift register chain by logic elements or embedded RAM modules. When using RAM module, the method does not consume any logic element for storing the value. Note that the shift register chain of input memory can be shared with different assertions and we can reduce the hardware resource significantly. We have checked the effectiveness of the proposed method using several assertions.

In the deep-submicron era, interconnect delays are becoming one of the most important factors that can affect performance in the VLSI design. Many state-of-the-art research in high level synthesis try to consider the effect of interconnect delays. These research indeed achieve better performance compared with traditional ones which ignore interconnect delays. When applications contain large loops, however, there is still much room to improve the performance by exploiting the parallelism. In this paper, we, for the first time, propose a method to utilize pipelining techniques and take interconnect delays into account together so as to improve the quality of high level synthesis. The proposed method has the following two characteristics: 1) it separates the consideration of interconnect delay from computation delay, and allows concurrent data transfer and computation; 2) it belongs to modulo scheduling framework, in the sense that all iterations have identical schedules, and are initiated periodically. We evaluate our method from two different points of view. Firstly, we compare our method with an existing interconnect-aware high level synthesis that does not utilize pipelining techniques, and the experimental results show that our method can obtain about 3.4 times performance improvement on average. Secondly, we compare our method with an existing pipeline synthesis that does not consider interconnect delays, and the results show that our method can obtain about 1.5 times performance improvement on average. In addition, we also evaluate our proposed architecture and the experimental results demonstrate that it is better than existing architecture in [1].

Inductive effect becomes important for on-chip global interconnects, like the power/ground (P/G) grid. Because of the locality property of partial reluctance, the inverse of partial inductance, the window-based partial reluctance extraction has been applied for large-scale interconnect structures. In this paper, an efficient method of partial reluctance extraction is proposed for large-scale regular P/G grid structures. With a block reuse technique, the proposed method makes full use of the structural regularity of the P/G grid. Numerical results demonstrate the proposed method is able to efficiently handle a P/G grid with up to one hundred thousands wire segments. It is several tens times faster than the window-based method, while generating accurate frequency-dependent partial reluctance and resistance.

The inflection S-shaped software reliability growth model (SRGM) proposed by Ohba (1984) is one of the well- known SRGMs. This paper deals with the optimal software release problem with regard to the expected software cost under this model based on the Bayesian approach. To reflect the effect of the learning experience for the updated software system, we consider several improvement factors to adjust the values of parameters characterizing the inflection S-shaped SRGM. Appropriate prior distributions are assumed for such factors and the expected total software cost is formulated. The optimal release time is shown to be finite and uniquely determined. Because of the flexibility of prior distributions, the proposed Bayesian methods may be applied in many different situations. Numerical results are presented on the basis of the real data.

Recently, Au et al. proposed a practical hierarchical identity-based encryption (HIBE) scheme and a hierarchical identity-based signature (HIBS) scheme. In this paper, we point out that there exists security weakness both for their HIBE and HIBS scheme. Furthermore, based on q-ABDHE, we present a new HIBE scheme which is proved secure in the standard model and it is also efficient. Compared with all previous HIBE schemes, ciphertext size as well as decryption cost are independent of the hierarchy depth. Ciphertexts in our HIBE scheme are always just four group elements and decryption requires only two bilinear map computations.

This paper proposes a method to construct a basis conversion matrix between two given bases in F_pm. In the proposed method, Gauss period normal basis (GNB) works as a bridge between the two bases. The proposed method exploits this property and construct a basis conversion matrix mostly faster than EDF-based algorithm on average in polynomial time. Finally, simulation results are reported in which the proposed method compute a basis conversion matrix within 30 msec on average with Celeron (2.00 GHz) when mlog p≈160.

Two-dimensional (2D) matrix symbols have higher storage capacity than conventional bar-codes, and hence have been used in various applications, including parts management in factories and Internet site addressing in camera-equipped mobile phones. These symbols generally utilize strong error control codes to protect data from errors caused by blots and scratches, and therefore require a large number of check bits. Because 2D matrix symbols are expressed in black and white dot patterns, blots and scratches often induce clusters of unidirectional errors (i.e., errors that affect black but not white dots, or vice versa). This paper proposes a new class of unidirectional l_m l_n-clustered error correcting codes capable of correcting unidirectional errors confined to a rectangle with l_m rows and l_n columns. The proposed code employs 2D interleaved parity-checks, as well as vertical and horizontal arithmetic residue checks. Clustered error pattern is derived using the 2D interleaved parity-checks, while vertical and horizontal positions of the error are calculated using the vertical and horizontal arithmetic residue checks. This paper also derives an upper bound on the number of codewords based on Hamming bound. Evaluation shows that the proposed code provides high code rate close to the bound. For example, for correcting a cluster of unidirectional 40 40 errors in 150 150 codeword, the code rate of the proposed code is 0.9272, while the upper bound is 0.9284.

In this letter, a pilot-less sampling frequency offset estimation scheme is presented for ultra-wideband orthogonal frequency division multiplexing (UWB-OFDM) systems. This scheme is based on the fact that two consecutive symbols convey the same information in the UWB-OFDM system, thus removing the need of pilot symbols. The performance of mean square error has been evaluated through simulation to verify the usefulness of the proposed scheme.

This letter presents a noise-robust sampling frequency offset (SFO) estimation scheme for OFDM-based WLAN systems. Mean square error of the proposed estimation scheme is derived and simulation results are provided to verify our analysis. The proposed SFO estimator has an improved performance over the existing schemes with a reduction of the estimation range.

This paper analyzes frequency tracking characteristics of a complex-coefficient adaptive infinite impulse response (IIR) notch filter with a simplified gradient-based algorithm. The input signal to the complex notch filter is a complex linear chirp embedded in a complex zero-mean white Gaussian noise. The analysis starts with derivation of a first-order real-coefficient difference equation with respect to steady-state instantaneous frequency tracking error. Closed-form expression for frequency tracking mean square error (MSE) is then derived from the difference equation. Lastly, closed-form expressions for optimum notch bandwidth coefficient and step size constant that minimize the frequency tracking MSE are derived. Computer simulations are presented to validate the analysis.

This paper presents a robust reduced order observer for a class of Lipschitz nonlinear systems with external disturbance. Sufficient conditions on the existence of the proposed observer are characterized by linear matrix inequalities. It is also shown that the proposed observer design can reduce the effect on the estimation error of external disturbance up to the prescribed level. Finally, a numerical example is provided to verify the proposed design method.

In this letter, we consider a problem of global stabilization of a class of approximately feedback linearized systems. We propose a new nonlinear control approach which includes a nonlinear controller and a Lyapunov-based design method. Our new nonlinear control approach broadens the class of systems under consideration over the existing results.

This paper presents two power-saving designs for Quadratic Polynomial Permutation (QPP) interleave address generator of which interleave length K is fixed and unfixed, respectively. These designs are based on our observation that the quadratic term f₂x²%K of f(x) = (f₁x+f₂x²)%K, which is the QPP address generating function, has a short period and is symmetric within the period. Power consumption is reduced by 27.4% in the design with fixed-K and 5.4% in the design with unfixed-K on the average for various values of K, when compared with existing designs.

Sanitizable signatures allow sanitizers to delete some pre-determined parts of a signed document without invalidating the signature. While ordinary sanitizable signatures allow verifiers to know how many subdocuments have been sanitized, invisibly sanitizable signatures do not leave any clue to the sanitized subdocuments; verifiers do not know whether or not sanitizing has been performed. Previous invisibly sanitizable signature scheme was constructed based on aggregate signature with pairings. In this article, we present the first invisibly sanitizable signature without using pairings. Our proposed scheme is secure under the RSA assumption.

Current Public Key Infrastructures suffer from a scaling problem, and some may have security problems, even given the topological simplification of bridge certification authorities. This paper analyzes the security problems in Bridge Certificate Authorities (BCA) model by using the concept of "impersonation risk," and proposes a new modified BCA model, which enhances its security, but is a bit more complex incertification path building and implementation than the existing one.

We propose an automatic generative method for stylus style CG as automatic generative method for non-photorealistic CG.