IEICE TRANSACTIONS on Fundamentals
Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages
Summary :
Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in manual routing. We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment. In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.6 pp.1433-1441
- Publication Date
- 2009/06/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.1433
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Keyword
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Yoichi TOMIOKA, Atsushi TAKAHASHI, "Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 6, pp. 1433-1441, June 2009, doi: 10.1587/transfun.E92.A.1433.
Abstract: Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in manual routing. We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment. In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1433/_p
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@ARTICLE{e92-a_6_1433,
author={Yoichi TOMIOKA, Atsushi TAKAHASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages},
year={2009},
volume={E92-A},
number={6},
pages={1433-1441},
abstract={Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in manual routing. We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment. In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.},
keywords={},
doi={10.1587/transfun.E92.A.1433},
ISSN={1745-1337},
month={June},}
Copy
TY - JOUR
TI - Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1433
EP - 1441
AU - Yoichi TOMIOKA
AU - Atsushi TAKAHASHI
PY - 2009
DO - 10.1587/transfun.E92.A.1433
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2009
AB - Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in manual routing. We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment. In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.
ER -
English
