In this paper, we propose a routing method for 2-layer ball grid array packages that generates a routing pattern satisfying a design rule. In our proposed method, the routing structure on each layer is restricted while keeping most of feasible patterns to efficiently obtain a feasible routing pattern. A routing pattern that satisfies the design rule is formulated as a mixed integer linear programming. In experiments with seven data, we obtain a routing pattern such that satisfies the design rule within a practical time by using a mixed integer linear programming solver.

Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in manual routing. We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment. In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.

Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and PCB, but it takes much time in manual routing. So the demand for automation of package routing is increasing. In this paper, we give the necessary and sufficient condition that all nets can be connected by monotonic routes when a net consists of a finger and a ball and fingers are on the two parallel boundaries of the Ball Grid Array package, and propose a monotonic routing method based on this condition. Moreover, we give a necessary condition and a sufficient condition when fingers are on the two orthogonal boundaries, and propose a monotonic routing method based on the necessary condition.

In this paper, we propose a global routing method for 2-layer BGA packages. In our routing model, the global routing for each net is uniquely determined by a via assignment of each net. Our global routing method starts from an initial monotonic via assignment and incrementally improves the via assignment to optimize the total wire length and the wire congestion. Experimental results show that our proposed method generates a better global routing efficiently.

First we introduce the high-frequency equivalent circuit model of the Fine Pitched Ball Grid Array (FPBGA) bonding for frequencies up to 20 GHz. The lumped circuit model of the FPBGA bonding was extracted based on S-parameters measurement and subsequent fitting of the model parameters. The test packages, which contain probing pads, coplanar waveguides and FPBGA ball bonding, were fabricated and measured. The suggested π-model of the FPBGA bonding consists of self-inductor, self-capacitor, and self-resistor components. From the extracted model, a solder ball of 350 µm diameter and 800 µm ball pitch has less than 0.08 nH self-inductance, 0.40 pF self capacitance, and about 10 mΩ self-resistance. In addition, the mutual capacitance caused by the presence of the adjacent bonding balls is included in the model. The FPBGA solder ball bonding has less than 1.5 dB insertion loss up to 20 GHz, and it causes negligible delay time in digital signal transmission. The extracted circuit model of FPBGA bonding is useful in design and performance simulation of advanced packages, which use FPBGA bonding.

Due to the large number of I/O's in a Ball-Grid-Array (BGA) package, routing becomes more and more an important work. A ring-based router for the BGA package is presented in this paper to interconnect each I/O pad of a chip to a corresponding ball distributed on the substrate area. The major phases for the router consist of layer assignment, topological routing, and physical routing. Using this router, we can generate an even distribution of planar and any-angle wires to improve manufacturing yield. We have also conducted various testing examples to verify the efficiency of this router. Experiments show that the router produces very good results, far better than the manual design, thus it can be applied to the practical packaging of integrated circuits.