In the field of adaptive notch filtering, Monotonically Increasing Gradient (MIG) algorithm has recently been proposed by Sugiura and Shimamura [1], where it is claimed that the MIG algorithm shows monotonically increasing gradient characteristics. However, our analysis has found that the underlying theory in [1] includes crucial errors. This letter shows that the formulation of the gradient characteristics in [1] is incorrect, and reveals that the MIG algorithm fails to realize monotonically increasing gradient characteristics when the input signal includes white noise.

Ordinal classification is a class of special tasks in machine learning and pattern recognition. As to ordinal classification, there is an ordinal structure among different decision values. The monotonicity constraint between features and decision should be taken into account as the fundamental assumption. However, in real-world applications, this assumption may be not true. Only some candidate features, instead of all, are monotonic with decision. So the existing feature selection algorithms which are designed for nominal classification or monotonic classification are not suitable for ordinal classification. In this paper, we propose a feature selection algorithm for ordinal classification based on considering the non-monotonic and monotonic features separately. We first introduce an assumption of hybrid monotonic classification consistency and define a feature evaluation function to calculate the relevance between the features and decision for ordinal classification. Then, we combine the reported measure and genetic algorithm (GA) to search the optimal feature subset. A collection of numerical experiments are implemented to show that the proposed approach can effectively reduce the feature size and improve the classification performance.

It is well known that an nth-order real polynomial D(z)= is Schur stable if its coefficients satisfy the monotonic condition, i.e., dn > dn-1 > > d1 > d0 > 0. In this letter it is shown that even if the monotonic condition is violated by one coefficient (say dk), D(z) is still Schur stable if the deviation of dk from dk+1 or dk-1 is not too large. More precisely we derive upper bounds for the admissible deviations of dk from dk+1 or dk-1 to ensure the Schur stability of D(z). It is also shown that the results obtained in this letter always yield the larger stability range for dk than an existing result.

An analytical method to make a trade off between tuning range and differential non-linearity (DNL) for a digitally controlled oscillator (DCO) is proposed. To verify the approach, a 12 bit DCO is designed, implemented in 0.18 µm CMOS technology, and tested. The measured DNL was -0.41 Least Significant Bit (LSB) without degrading other parameters which is the best so far among the reported DCOs.

In this paper, we propose a routing method for 2-layer ball grid array packages that generates a routing pattern satisfying a design rule. In our proposed method, the routing structure on each layer is restricted while keeping most of feasible patterns to efficiently obtain a feasible routing pattern. A routing pattern that satisfies the design rule is formulated as a mixed integer linear programming. In experiments with seven data, we obtain a routing pattern such that satisfies the design rule within a practical time by using a mixed integer linear programming solver.

Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in manual routing. We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment. In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.

Monotonic condition, a well-known sufficient condition for Schur stability of real polynomials, is relaxed. The condition reads that a series of strictly and monotonically decreasing positive coefficients of the polynomials yields Schur stability. It is shown by inspecting the original proof that equalities are allowed in all the inequalities but two which are located at appropriate positions.

Yubazaki et al. have proposed "single input rule modules connected type fuzzy reasoning method" (SIRMs method, for short) whose final output is obtained by summarizing the product of the importance degrees and the inference results from single input fuzzy rule module. Another type of single input type fuzzy reasoning method proposed by Hayashi et al. (we call it "Single Input Connected fuzzy reasoning method" (SIC method, for short) in this paper) uses rule modules to each input item as well as SIRMs method. We expect that inference results of SIRMs method and SIC method have monotonicity if the antecedent parts and consequent parts of fuzzy rules in SIRMs rule modules have monotonicity. However, this paper points out that even if fuzzy rules in SIRMs rule modules have monotonicity, the inference results do not necessarily have monotonicity. Moreover, it clarifies the conditions for the monotonicity of inference results by SIRMs method and SIC method.

Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and PCB, but it takes much time in manual routing. So the demand for automation of package routing is increasing. In this paper, we give the necessary and sufficient condition that all nets can be connected by monotonic routes when a net consists of a finger and a ball and fingers are on the two parallel boundaries of the Ball Grid Array package, and propose a monotonic routing method based on this condition. Moreover, we give a necessary condition and a sufficient condition when fingers are on the two orthogonal boundaries, and propose a monotonic routing method based on the necessary condition.

A hard real-time system is one whose correctness depends not only on the logical result, but also when the results are produced. While many techniques have been proposed for single processor real-time systems, multiprocessor systems have not been studied so extensively. In this paper, we mainly propose two variant (DCTS) by using the Early-Release-Fair (ERfair) and Proportionate-fair (Pfair) model with integral assumptions for identical multi-processor real-time systems. ERfair is a scheduling model for real-time tasks on a multiprocessor system. On the different definitions of distance constraint, we propose two efficient scheduling algorithms designed to probe whether the distance constraints of all ER-fair tasks can be guaranteed. If the distance constraints cannot be guaranteed, then the proposed algorithms gather the unfeasible tasks and inflate them with a reweighting function. The proposed algorithms are linear-time and most suitable for dynamic systems. The experimental results reveal that the proposed algorithms increase significantly the ratio of schedulable task sets.

In this paper, we propose a global routing method for 2-layer BGA packages. In our routing model, the global routing for each net is uniquely determined by a via assignment of each net. Our global routing method starts from an initial monotonic via assignment and incrementally improves the via assignment to optimize the total wire length and the wire congestion. Experimental results show that our proposed method generates a better global routing efficiently.

We describe a new inconsistent case which is susceptible to occur while producing consistent answer set using prioritized default logic. We define new semantics for prioritized default logic in order to solve this problem. There is a sign difference between General and Extended logic programs. Extended logic programs are formulated using classical negation, For this reason, an inconsistent answer set can sometimes be produced. For the most part, default reasoning semantics successfully resolved this problem, but a conflict could still arise in one particular case. The purpose of this paper is to present this eventuality, and revise the semantics of default logic in order to give an answer to this problem.

The hardware implementation of a neural network model using stochastic logic has been able to integrate numerous neuron units on a chip. However, the limitation of applications occurred since the stochastic neurosystem could execute only discrete-time dynamics. We have contrived a neuron model with continuous-time dynamics by using stochastic calculations. In this paper, we propose the circuit design of a new neuron circuit, and show the fabricated neurochip comprising 64 neurons with experimental results. Furthermore, a new asynchronous updating method and a new activation function circuit are proposed. These improvements enhance the performance of the neurochip greatly.

An IIR digital low pass filter with flat monotonic passband, equiripple stopband and narrower transition bandwidth than that of Inverse Chebyshev digital filters of the same order is designed. The requisite equiripple stopband is realized by designing the filter in Deczkeys' w-plane. The characteristic functions are designed so as to have a root of multiplicity n at ω = 0 to ensure the n degree of flatness of the passband, and to have a pair of complex conjugate roots with coordinates constrained such that the magnitude response of the passband attenuates monotonically. The freedom in the coordinate of the complex conjugate roots is exploited to minimize the transition bandwidth. The equations are derived that give the minimum transition bandwidth of the proposed filter, which is considerably narrower than that of Inverse Chebyshev filters. It is showen through practical numerical examples that the order of the proposed filter is as low as half that of the Inverse Chebyshev filter satisfying the same specification.

The knowledge of a good enclosure of the range of a function over small interval regions allows us to avoid convergence of optimization algorithms to a non-global point(s). We used interval slopes f[X,x] to check for monotonicity and integrated their derivative forms g[X,x], x X by quadratic and Newton methods to obtain narrow enclosures. In order to include boundary points in the search for the optimum point(s), we expanded the initial box by a small width on each dimension. These procedures resulted in an improvement in the algorithm proposed by Hansen.

Effects of high-frequency cyclic input and noise on interspike intervals in the coupled Bonhoeffer-van der Pol (BVP) model are studied with computer simulation. When two BVP elements are weakly coupled and cyclic input or noise is added to the first element, the interspike intervals of the second element decrease non-monotonically as the amplitude of the input increases. Further, complicated bifurcations in the interspike intervals are caused by cyclic input in the coupled BVP model in the oscillating state. Effects of the coupling on small rotations due to noise and the interruption of oscillations due to cyclic input, which occur when the equilibrium point is close to the critical point, are also studied. The non-monotonic changes and bifurcations in the interspike intervals are attributed to the phase locking of the coupled elements.

A very low-power, high-speed flash A/D converter front-end composed of a new latched comparator was developed. We established a butterfly sorting technique to guarantee the monotonicity of the converter. The 6-bit A/D front-end achieves a speed of 100 Msps and dynamic range of 33 dB with power consumption of only 7 mW at the supply voltage of 1 V, and the butterfly sorter guarantees 6-bit monotonicity with an extra power consumption of 1 mW.

In this paper, we report a study on hardware implementation of a Deterministic Boltzmann Machine (DBM) with non-monotonic neurons (non-monotonic DBM network). The hardware DBM network has fewer components than other neural networks. Results from numerical simulations show that the non-monotonic DBM network has high learning ability as compared to the monotonic DBM network. These results show that the non-monotonic DBM network has large potential for the implementation of a high functional neurochip. Then, we design and fabricate a neurochip of the non-monotonic DBM network of which measurement confirms that the high-functional large-scale neural system can be realized on a compact neurochip by using the non-monotonic neurons.

An ATMS (Assumption-based Truth Maintenance System) has been widely used for maintaining the truth of an information by detecting and solving the contradictions in rule-based systems. However, the ATMS cannot correctly maintain the truth of the information in case that the generated information is satisfied within a time interval or includes data about temporal relations of events in time varying situations, because it has no mechanism manipulating temporal data. In this paper, we propose the extended ATMS that can maintain the truth of the information in the knowledge-based system using information changing over time or temporal relations of events. To maintain the contexts generated by relations of events, we modify the label representation method, the disjunction and conjunction simplification method in the label-propagation procedure and the nogood handling method of the conventional ATMS.

In this paper, we focus on regularity and set-valued functions. Regularity was first introduced by S. C. Kleene in the propositional operations of his ternary logic. Then, M. Mukaidono investigated some properties of ternary functions, which can be represented by regular operations. He called such ternary functions "regular ternary logic functions". Regular ternary logic functions are useful for representing and analyzing ambiguities such as transient states or initial states in binary logic circuits that Boolean functions cannot cope with. Furthermore, they are also applied to studies of fail-safe systems for binary logic circuits. In this paper, we will discuss an extension of regular ternary logic functions into r-valued set-valued functions, which are defined as mappings on a set of nonempty subsets of the r-valued set {0, 1, . . . , r-1}. First, the paper will show a method by which operations on the r-valued set {0, 1, . . . , r-1} can be expanded into operations on the set of nonempty subsets of {0, 1, . . . , r-1}. These operations will be called regular since this method is identical with the way that Kleene expanded operations of binary logic into his ternary logic. Finally, explicit expressions of set-valued functions monotonic in subset will be presented.