Interacting Self-Timed Pipelines and Elementary Coupling Control Modules
Summary :
The self-timed pipeline (STP) is one of the most promising VLSI/SoC architectures. It achieves efficient utilization of tens of billions of transistors, consumes ultra low power, and is easy-to-design because of its signal integrity and low electro-magnetic interference. These basic features of the STP have been proven by the development of self-timed data-driven multimedia processors, DDMP's. This paper proposes a novel scheme of interacting self-timed (clockless) pipelines by which the various distributed and interconnected pipelines can achieve highly functional stream processing in future giga-transistor chips. The paper also proposes a set of elementary coupling control modules that facilitate various combinations of flow-thru processing between pipelines, and then discusses the practicality of the proposed scheme through the LSI design of application modules such as a priority-based queue, a mutual interconnection network, and a pipelined sorter.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.7 pp.1642-1651
- Publication Date
- 2009/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.1642
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Kazuhiro KOMATSU, Shuji SANNOMIYA, Makoto IWATA, Hiroaki TERADA, Suguru KAMEDA, Kazuo TSUBOUCHI, "Interacting Self-Timed Pipelines and Elementary Coupling Control Modules" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 7, pp. 1642-1651, July 2009, doi: 10.1587/transfun.E92.A.1642.
Abstract: The self-timed pipeline (STP) is one of the most promising VLSI/SoC architectures. It achieves efficient utilization of tens of billions of transistors, consumes ultra low power, and is easy-to-design because of its signal integrity and low electro-magnetic interference. These basic features of the STP have been proven by the development of self-timed data-driven multimedia processors, DDMP's. This paper proposes a novel scheme of interacting self-timed (clockless) pipelines by which the various distributed and interconnected pipelines can achieve highly functional stream processing in future giga-transistor chips. The paper also proposes a set of elementary coupling control modules that facilitate various combinations of flow-thru processing between pipelines, and then discusses the practicality of the proposed scheme through the LSI design of application modules such as a priority-based queue, a mutual interconnection network, and a pipelined sorter.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.1642/_p
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@ARTICLE{e92-a_7_1642,
author={Kazuhiro KOMATSU, Shuji SANNOMIYA, Makoto IWATA, Hiroaki TERADA, Suguru KAMEDA, Kazuo TSUBOUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Interacting Self-Timed Pipelines and Elementary Coupling Control Modules},
year={2009},
volume={E92-A},
number={7},
pages={1642-1651},
abstract={The self-timed pipeline (STP) is one of the most promising VLSI/SoC architectures. It achieves efficient utilization of tens of billions of transistors, consumes ultra low power, and is easy-to-design because of its signal integrity and low electro-magnetic interference. These basic features of the STP have been proven by the development of self-timed data-driven multimedia processors, DDMP's. This paper proposes a novel scheme of interacting self-timed (clockless) pipelines by which the various distributed and interconnected pipelines can achieve highly functional stream processing in future giga-transistor chips. The paper also proposes a set of elementary coupling control modules that facilitate various combinations of flow-thru processing between pipelines, and then discusses the practicality of the proposed scheme through the LSI design of application modules such as a priority-based queue, a mutual interconnection network, and a pipelined sorter.},
keywords={},
doi={10.1587/transfun.E92.A.1642},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - Interacting Self-Timed Pipelines and Elementary Coupling Control Modules
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1642
EP - 1651
AU - Kazuhiro KOMATSU
AU - Shuji SANNOMIYA
AU - Makoto IWATA
AU - Hiroaki TERADA
AU - Suguru KAMEDA
AU - Kazuo TSUBOUCHI
PY - 2009
DO - 10.1587/transfun.E92.A.1642
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2009
AB - The self-timed pipeline (STP) is one of the most promising VLSI/SoC architectures. It achieves efficient utilization of tens of billions of transistors, consumes ultra low power, and is easy-to-design because of its signal integrity and low electro-magnetic interference. These basic features of the STP have been proven by the development of self-timed data-driven multimedia processors, DDMP's. This paper proposes a novel scheme of interacting self-timed (clockless) pipelines by which the various distributed and interconnected pipelines can achieve highly functional stream processing in future giga-transistor chips. The paper also proposes a set of elementary coupling control modules that facilitate various combinations of flow-thru processing between pipelines, and then discusses the practicality of the proposed scheme through the LSI design of application modules such as a priority-based queue, a mutual interconnection network, and a pipelined sorter.
ER -
English
