IEICE TRANSACTIONS on Fundamentals
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
Summary :
In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.12 pp.3143-3150
- Publication Date
- 2009/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.3143
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-Level Synthesis and System-Level Design
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Ya-Shih HUANG, Yu-Ju HONG, Juinn-Dar HUANG, "Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3143-3150, December 2009, doi: 10.1587/transfun.E92.A.3143.
Abstract: In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3143/_p
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@ARTICLE{e92-a_12_3143,
author={Ya-Shih HUANG, Yu-Ju HONG, Juinn-Dar HUANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture},
year={2009},
volume={E92-A},
number={12},
pages={3143-3150},
abstract={In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.},
keywords={},
doi={10.1587/transfun.E92.A.3143},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3143
EP - 3150
AU - Ya-Shih HUANG
AU - Yu-Ju HONG
AU - Juinn-Dar HUANG
PY - 2009
DO - 10.1587/transfun.E92.A.3143
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.
ER -
English
