Entropy Decoding Processor for Modern Multimedia Applications

Sumek WISAYATAKSIN; Dongju LI; Tsuyoshi ISSHIKI; Hiroaki KUNIEDA

doi:10.1587/transfun.E92.A.3248

Entropy Decoding Processor for Modern Multimedia Applications

Sumek WISAYATAKSIN, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA

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An entropy decoding engine plays an important role in modern multimedia decoders. Previous researches that focused on the decoding performance paid a considerable attention to only one parameter such as the data parsing speed, but they did not consider the performance caused by a table configuration time and memory size. In this paper, we developed a novel method of entropy decoding based on the two step group matching scheme. Our approach achieves the high performance on both data parsing speed and configuration time with small memory needed. We also deployed our decoding scheme to implement an entropy decoding processor, which performs operations based on normal processor instructions and VLD instructions for decoding variable length codes. Several extended VLD instructions are prepared to increase the bitstream parsing process in modern multimedia applications. This processor provides a solution with software flexibility and hardware high speed for stand-alone entropy decoding engines. The VLSI hardware is designed by the Language for Instruction Set Architecture (LISA) with 23 Kgates and 110 MHz maximum clock frequency under TSMC 0.18 µm technology. The experimental simulations revealed that proposed processor achieves the higher performance and suitable for many practical applications such as MPEG-2, MPEG-4, H.264/AVC and AAC.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.12 pp.3248-3257

Publication Date: 2009/12/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E92.A.3248

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Embedded, Real-Time and Reconfigurable Systems

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Sumek WISAYATAKSIN, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, "Entropy Decoding Processor for Modern Multimedia Applications" in IEICE TRANSACTIONS on Fundamentals, vol. E92-A, no. 12, pp. 3248-3257, December 2009, doi: 10.1587/transfun.E92.A.3248.
Abstract: An entropy decoding engine plays an important role in modern multimedia decoders. Previous researches that focused on the decoding performance paid a considerable attention to only one parameter such as the data parsing speed, but they did not consider the performance caused by a table configuration time and memory size. In this paper, we developed a novel method of entropy decoding based on the two step group matching scheme. Our approach achieves the high performance on both data parsing speed and configuration time with small memory needed. We also deployed our decoding scheme to implement an entropy decoding processor, which performs operations based on normal processor instructions and VLD instructions for decoding variable length codes. Several extended VLD instructions are prepared to increase the bitstream parsing process in modern multimedia applications. This processor provides a solution with software flexibility and hardware high speed for stand-alone entropy decoding engines. The VLSI hardware is designed by the Language for Instruction Set Architecture (LISA) with 23 Kgates and 110 MHz maximum clock frequency under TSMC 0.18 µm technology. The experimental simulations revealed that proposed processor achieves the higher performance and suitable for many practical applications such as MPEG-2, MPEG-4, H.264/AVC and AAC.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3248/_p

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@ARTICLE{e92-a_12_3248,
author={Sumek WISAYATAKSIN, Dongju LI, Tsuyoshi ISSHIKI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Entropy Decoding Processor for Modern Multimedia Applications},
year={2009},
volume={E92-A},
number={12},
pages={3248-3257},
abstract={An entropy decoding engine plays an important role in modern multimedia decoders. Previous researches that focused on the decoding performance paid a considerable attention to only one parameter such as the data parsing speed, but they did not consider the performance caused by a table configuration time and memory size. In this paper, we developed a novel method of entropy decoding based on the two step group matching scheme. Our approach achieves the high performance on both data parsing speed and configuration time with small memory needed. We also deployed our decoding scheme to implement an entropy decoding processor, which performs operations based on normal processor instructions and VLD instructions for decoding variable length codes. Several extended VLD instructions are prepared to increase the bitstream parsing process in modern multimedia applications. This processor provides a solution with software flexibility and hardware high speed for stand-alone entropy decoding engines. The VLSI hardware is designed by the Language for Instruction Set Architecture (LISA) with 23 Kgates and 110 MHz maximum clock frequency under TSMC 0.18 µm technology. The experimental simulations revealed that proposed processor achieves the higher performance and suitable for many practical applications such as MPEG-2, MPEG-4, H.264/AVC and AAC.},
keywords={},
doi={10.1587/transfun.E92.A.3248},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Entropy Decoding Processor for Modern Multimedia Applications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3248
EP - 3257
AU - Sumek WISAYATAKSIN
AU - Dongju LI
AU - Tsuyoshi ISSHIKI
AU - Hiroaki KUNIEDA
PY - 2009
DO - 10.1587/transfun.E92.A.3248
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - An entropy decoding engine plays an important role in modern multimedia decoders. Previous researches that focused on the decoding performance paid a considerable attention to only one parameter such as the data parsing speed, but they did not consider the performance caused by a table configuration time and memory size. In this paper, we developed a novel method of entropy decoding based on the two step group matching scheme. Our approach achieves the high performance on both data parsing speed and configuration time with small memory needed. We also deployed our decoding scheme to implement an entropy decoding processor, which performs operations based on normal processor instructions and VLD instructions for decoding variable length codes. Several extended VLD instructions are prepared to increase the bitstream parsing process in modern multimedia applications. This processor provides a solution with software flexibility and hardware high speed for stand-alone entropy decoding engines. The VLSI hardware is designed by the Language for Instruction Set Architecture (LISA) with 23 Kgates and 110 MHz maximum clock frequency under TSMC 0.18 µm technology. The experimental simulations revealed that proposed processor achieves the higher performance and suitable for many practical applications such as MPEG-2, MPEG-4, H.264/AVC and AAC.
ER -