This paper proposes an efficient FFT algorithm for the Psycho-Acoustic Model (PAM) of MPEG-4 AAC. The proposed algorithm synthesizes FFT coefficients using MDCT and MDST coefficients through circular convolution. The complexity of the MDCT and MDST coefficients is approximately half of the original FFT. We also design a new PAM based on the proposed FFT algorithm, which has 15% lower computational complexity than the original PAM without degradation of sound quality. Subjective as well as objective test results are presented to confirm the efficiency of the proposed FFT computation algorithm and the PAM.

An entropy decoding engine plays an important role in modern multimedia decoders. Previous researches that focused on the decoding performance paid a considerable attention to only one parameter such as the data parsing speed, but they did not consider the performance caused by a table configuration time and memory size. In this paper, we developed a novel method of entropy decoding based on the two step group matching scheme. Our approach achieves the high performance on both data parsing speed and configuration time with small memory needed. We also deployed our decoding scheme to implement an entropy decoding processor, which performs operations based on normal processor instructions and VLD instructions for decoding variable length codes. Several extended VLD instructions are prepared to increase the bitstream parsing process in modern multimedia applications. This processor provides a solution with software flexibility and hardware high speed for stand-alone entropy decoding engines. The VLSI hardware is designed by the Language for Instruction Set Architecture (LISA) with 23 Kgates and 110 MHz maximum clock frequency under TSMC 0.18 µm technology. The experimental simulations revealed that proposed processor achieves the higher performance and suitable for many practical applications such as MPEG-2, MPEG-4, H.264/AVC and AAC.

Scalable video coding (SVC) was standardized as an extension of H.264/AVC by the JVT (Joint Video Team) in Nov. 2007. The biggest feature of SVC is multi-layered coding where two or more video sequences are compressed into a single bit-stream. This letter proposes a fast block mode decision algorithm in spatial enhancement layer of SVC. The proposed algorithm achieves early decision by limiting the number of candidate modes for block with certain characteristic called same motion vector block (SMVB). Our proposed method reduces the complexity, in terms of encoding time by up to 66.17%. Nevertheless, it shows negligible PSNR degradation by only up to 0.16 dB and increases the bit-rate by only up to 0.64%, respectively.

A new linear prediction analysis method for multichannel signals was devised, with the goal of enhancing the compression performance of the MPEG-4 Audio Lossless Coding (ALS) compliant encoder and decoder. The multichannel coding tool for this standard carries out an adaptively weighted subtraction of the residual signals of the coding channel from those of the reference channel, both of which are produced by independent linear prediction. Our linear prediction method tries to directly minimize the amplitude of the predicted residual signal after subtraction of the signals of the coding channel, and the method has been implemented in the MPEG-4 ALS codec software. The results of a comprehensive evaluation show that this method reduces the size of a compressed file. The maximum improvement of the compression ratio is 14.6% which is achieved at the cost of a small increase in computational complexity at the encoder and without increase in decoding time. This is a practical method because the compressed bitstream remains compliant with the MPEG-4 ALS standard.

In this letter, we propose an enhanced method for inter-layer motion prediction in scalable video coding (SVC). For inter-layer motion prediction, the use of refined motion data in the Fine Granular Scalability (FGS) layer is proposed instead of the conventional use of motion data in the base quality layer to reduce the inter-layer redundancy efficiently. Experimental results show that the proposed method enhances coding efficiency without increasing the computational complexity of the decoder.

Transmitting multimedia data requires high bandwidth and low delay of the network. Today's wireless networks satisfy these requirements in ideal situations, but in practice multiple devices including those of neighboring networks share the same physical layer channel and the desired speeds in the wireless network can not be achieved. Traffic in one network causes interference to other neighboring networks. In this paper, we evaluate end user's playback quality of video content transmitted over a wireless network. We take into account the influence of interference from a neighboring network and define a multi-layer control strategy to maintain the quality on the network. Through simulations, we have obtained acceptable improvements in video playback quality by controlling the transmission power, the number of retransmissions, and other parameters at various layers.

This paper briefly introduces the T-DMB standard based on Eureka-147 DAB and presents a new T-DMB transmission system, which uses a device called the Ensemble Remultiplexer, for mobile multimedia broadcasting service. And we verify the T-DMB standard by using the new transmission system with commercial equipment in the laboratory and in the field as moving on a car in high speed around urban districts surrounded by high buildings.

Power efficiency and real-time processing capability are two major issues in today's mobile video applications. We proposed a novel Motion Estimation (ME) engine for power-efficient real-time MPEG-4 video coding based on our previously proposed content-based ME algorithm [8],[13]. By adopting Full Search (FS) and Three Step Search (TSS) alternatively according to the nature of video contents, this algorithm keeps the visual quality very close to that of FS with only 3% of its computational power. We designed a flexible Block Matching (BM) Unit with 16-PE SIMD data path so that the adaptive ME can be performed at a much lower clock frequency and hardware cost as compared with previous FS based work. To reduce the energy cost caused by excessive external memory access, on-chip SRAM is also utilized and optimized for parallel processing in the BM Unit. The ME engine is fabricated with TSMC 0.18 µm technology. When processing QCIF (15 fps) video, the estimated power is 2.88 mW@4.16 MHz (supply voltage: 1.62 V). It is believed to be a favorable contribution to the video encoder LSI design for mobile applications.

The module-wise dynamic voltage and frequency scaling (MDVFS) scheme is applied to a single-chip H.264/MPEG-4 audio/visual codec LSI. The power consumption of the target module with controlled supply voltage and frequency is reduced by 40% in comparison with the operation without voltage or frequency scaling. The consumed power of the chip is 63 mW in decoding QVGA H.264 video at 15 fps and MPEG-4 AAC LC audio simultaneously. This LSI keep operating continuously even during the voltage transition of the target module by introducing the newly developed dynamic de-skewing system (DDS) which watches and control the clock edge of the target module.

This paper provides a performance evaluation of our audio and video CODEC by using a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with a SPXK5SC DSP core in order to evaluate the overall performance of audio/video CODEC on a target system. Our emulation system using a DSP core TEG, which has a bus interface, and an FPGA is suitable for overall system evaluation on real-time workloads as well as architectural investigation. In this paper, we discuss the use of the emulation system in evaluating performance during AV CODEC execution. In addition, an architecture design based on our emulation system is also described.

In this paper, we present an MPEG-4 decoding scheme based on reversible variable length code. The scheme is purely decoder based and compliance with the standard is fully maintained. Moreover, the data recovery scheme suggested in MPEG-4 can still be used as the default scheme. Simulation results show that the proposed scheme achieves better data recovery, both in terms of PSNR and perceptual quality, from error propagation region of a corrupted video packet, as compared to existing MPEG-4 scheme.

In this paper, a new error concealment algorithm for MPEG-4 object-based video is presented. The algorithm consists of a feature matching step to identify temporally corresponding features between video frames and an affine parameter estimation step to find the motion of the feature points. In the feature matching step, an efficient cross-radial search (CRS) method is developed to find the best matching points. In the affine parameter estimation step, a non-iterative least squares estimation algorithm is developed to estimate the affine parameters. An attractive feature of the algorithm is that the shape data and texture data are handled by the same method. Unlike previous methods, this unified approach works for the case where the video object undergoes a drastic movement, such as a sharp turn. Experimental results show that the proposed algorithm performs much better than previous approaches by about 0.3-2.8 dB for shape data and 1.6-5.0 dB for texture data.

We consider the edge-linking approach for accurate locating of moving object boundaries in video segmentation. We review the existing methods and propose a scheme designed for efficiency and better accuracy. The scheme first obtains a very rough outline of an object by a suitable means, e.g., change detection. It then forms a relatively compact image region that properly contains the object, through a procedure termed "mask sketch." Finally, the outermost edges in the region are found and linked via a shortest-path algorithm. Experiments show that the scheme yields good performance.

This paper introduces a new frame-based bit-rate control scheme for bandwidth-adaptive video coding. Proposed method can accurately adapt to the rapid varying scene characteristics by reducing the number of occurrences of the extrapolations while updating the rate-distortion model used for determine the appropriate quantization steps.

In this paper, we propose an optimal bit rate control algorithm which is fully compatible with MPEG-4 or H.263+. The proposed algorithm is designed to identify the optimal quantizer set through Lagrangian optimization when used for optimal bit allocation. To find the optimal quantizer set, we make use of the Viterbi algorithm in order to solve the dependency between quantization parameters of each macroblock due to the unique characteristics of MPEG-4 or H.263+. We set the Lagrangian cost function as a cost function of the Viterbi algorithm. We implement the proposed algorithm in MPEG-4 coders and compare its performance to the VM8 and optimal bit rate control algorithm, using independent quantization parameters in the circumstance of a low bit rate.

A single chip processor suitable for various multimedia communication products has been developed. This chip achieves real-time bi-directional encoding/decoding for CIF resolution video at a frame rate of 30 fr/s, and meets such standards, as H.320 and H.324. The chip is composed of a video-processing unit for MPEG-4 and H.26X standards, a DSP unit for speech codec and multiplex processes, and a RISC unit for managing the whole chip. By heterogeneous multiple processor architecture, careful study of task sharing for each processing unit and bus configuration, a single chip solution can be achieved with reasonable operation speed and low-power consumption suitable for consumer products. Moreover, by applying an original video processing unit architecture, this chip achieves real-time bi-directional encoding/decoding for CIF-resolution video at a frame rate of 30 fr/s. An original video bus was developed to provide high performance and low-power consumption while sharing one external memory which is necessary for various video processes and graphics functions. This shared memory also has the effect of minimizing die size and I/O ports. This chip has been fabricated with 4-metal 0.18 µm CMOS technology to produce a chip area of 10.510.5 mm2 with 1.2 W power dissipation including I/O power, at 1.8 V for internal supply and 3.3 V for I/O power supply.

We present a single-chip MPEG-4 audiovisual LSI in a 0.13 µm CMOS, 5-layer metal technology with 16 Mbit embedded DRAM, which integrates four 16 bit RISC and dedicated hardware accelerators including a 5 GOPS post filtering unit. It consumes 160 mW at 125 MHz and dissipates 80 nA in the standby mode. The chip is the world first LSI handling MPEG-4 CIF video encoding at 15 frames/sec and audio/speech encoding simultaneously.

Although watermarking techniques have been extensively developed for natural videos, little progress is made in the area of graphics animation. Following the former successful MPEG-1 and MPEG-2 coding standards that provide efficient representations of natural videos, the emerging MPEG-4 standard incorporates new coding tools for 2D mesh animation. Graphics animation information is crucial for many applications and may need proper protection. In this paper, we develop a watermarking technique suitable for MPEG-4 2D mesh animation. The proposed method is based on the multiresolution analysis of 2D dynamic mesh. We perform wavelet transform on the temporal sequence of the node points to extract the significant spectral components of mesh movement, which we term the "feature motions. " A binary watermark invisibly resides in the feature motions based on the spread-spectrum principle. Before watermark detection, a spatial-domain least-squares registration technique is used to restore the possibly geometrically distorted mesh data. Each watermark bit is then detected by hard decision with cryptographically secure keys. We have tested the proposed method with a variety of attacks, including affine transformations, temporal smoothing, spectral enhancement and attenuation, additive random noise, and a combination of the above. Experimental results show that the proposed watermarks can withstand the aforementioned attacks.

Video transmission over Terrestrial Trunked Radio (TETRA) mobile channel employing MPEG-4 visual coding standard is proposed in this paper. Detail parameters of the proposed systems are discussed in this paper. Performance of the proposed systems was evaluated in Average Peak Signal to Noise Ratio (APSNR) versus Signal to Noise Ratio (SNR) and Bit Error Rate (BER). In particular, the video quality that can be achieved at different channel conditions and employing different combinations of MPEG-4 visual error resilient tools is presented in this paper. Results obtained show that higher video bitrate does not necessarily lead to higher video quality at the receiver as the received video quality depends on the bit error pattern or the number of error free video packets.

We propose an efficient motion estimation algorithm to search an additional area according to the motion of a camcorder, which is obtained from a gyro sensor. When the camcorder moves, the background moves in the opposite direction. The proposed algorithm searches three regions, one around the center, another around the predicted region and another in the background around the region associated with the camcorder motion. Compared to conventional algorithms without the last region, the proposed one reduces the amount of computation to 1/5 while maintaining or enhancing the quality.