This paper presents media processor architectures for automotive applications. Media processing applications with their requirements for LSI implementations are first described for vision based driver assistance as well as graphical user interface for car navigation using 3D graphics. Then, parallel processing architectures for vision and graphics in these applications are reviewed with their performance and cost. After that, future trends of automotive media processing such as integration of vision and 3D graphics functions are shown with their applications and the required performance. Moreover, parallel processing architectures are discussed for the integration of vision and graphics. Finally, an prospect of a next-generation media processing LSI for automotives is provided.

This paper provides a performance evaluation of our audio and video CODEC by using a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with a SPXK5SC DSP core in order to evaluate the overall performance of audio/video CODEC on a target system. Our emulation system using a DSP core TEG, which has a bus interface, and an FPGA is suitable for overall system evaluation on real-time workloads as well as architectural investigation. In this paper, we discuss the use of the emulation system in evaluating performance during AV CODEC execution. In addition, an architecture design based on our emulation system is also described.

This paper describes a 51.2 GOPS video recognition processor that provides a cost effective device solution for vision-based intelligent cruise control (ICC) applications. By integrating 128 4-way VLIW (Very Low Instruction Word) processing elements and operating at 100 MHz, the processor achieves to provide a computation power enough for a weather robust lane mark and vehicle detection function written in a high level programming language, to run in video rate, while at the same time it satisfies power efficiency requirements of an in-vehicle LSI. Basing on four basic parallel methods and a software environment including an optimizing compiler of an extended C language and video-based GUI tools, efficient development of real-time video recognition applications that effectively utilize the 128 processing elements are facilitated. Benchmark results show that, this processor can provide a four times better performance compared with a 2.4 GHz general purpose micro-processor.

This paper presents a multimedia architecture extension design for a 200-MHz, 1.6-GOPS embedded RISC processor. The datapath architecture of the processor which realizes parallel execution of data transfer and SIMD (single instruction stream multiple data stream) parallel arithmetic operations is designed. Four SIMD parallel 16-bit MAC (multiply-accumulation) instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 16-bit accumulation. This parallel 16-bit MAC on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as the correlation and the matrix-vector multiplications in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, a 2D-IDCT which satisfies the IEEE1180 can be implemented in 202 cycles.

A novel scheduling method for asynchronous multirate/multi-task processing by programmable digital signal processors (DSPs) has been developed. This mixed scheduling method combines static and dynamic scheduling, and avoids runtime overheads due to interrupts in context switching to realizes asynchronous multirate systems. The processing delay introduced when using static scheduling with static buffering is avoided by introducing deadline scheduling in the static schedule design. In the developed software design system, a block-diagram description language is extended to describe asynchronous multi-task processing. The scheduling method enables asynchronous multirate processing, such as arbitrary-sampling-ratio rate conversion, asynchronous interface, and multimedia applications, to be efficiently realized by programmable DSPs.

This paper presents adaptive image enhancement algorithms which enhance hidden signals in the pictures and describes their implementation for real-time video signals. An image enhancement algorithm proposed by T. Peli and J. S. Lim is extended for application to video signals. A fast implementation algorithm is provided with parallel implementation. The proposed algorithms are shown to be realized in real-time on 200 MHz microprocessors with multimedia extensions for 720 480 (pixels) 30 frames/sec video signals.

This paper introduces fast methods for variable length decoding (VLD) and inverse quantization (IQ) on software MPEG-2 decoders by using Single Instruction stream Multiple Data stream (SIMD) type instructions for multimedia applications. With the VLD implementation, the VLD tables are made as small as possible so as to minimize missed cache accesses, and variable length codewords are decoded concurrently. With the IQ implementation, inverse quantization of the VLD results is performed in parallel. When these methods are used, combined clock cycles for VLD and IQ are roughly 30% shorter than those resulting from conventional methods, and this effect is especially pronounced for high bitrate streams.