IEICE TRANSACTIONS on Information
Performance Evaluation of the AV CODEC on a Low-Power SPXK5SC DSP Core
Summary :
This paper provides a performance evaluation of our audio and video CODEC by using a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with a SPXK5SC DSP core in order to evaluate the overall performance of audio/video CODEC on a target system. Our emulation system using a DSP core TEG, which has a bus interface, and an FPGA is suitable for overall system evaluation on real-time workloads as well as architectural investigation. In this paper, we discuss the use of the emulation system in evaluating performance during AV CODEC execution. In addition, an architecture design based on our emulation system is also described.
- Publication
- IEICE TRANSACTIONS on Information Vol.E88-D No.6 pp.1224-1230
- Publication Date
- 2005/06/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietisy/e88-d.6.1224
- Type of Manuscript
- PAPER
- Category
- Image Processing and Video Processing
Authors
Takahiro KUMURA
Norio KAYAMA
Shinichi SHIONOYA
Kazuo KUMAGIRI
Takao KUSANO
Makoto YOSHIDA
Masao IKEKAWA
Ichiro KURODA
Takao NISHITANI
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Takahiro KUMURA, Norio KAYAMA, Shinichi SHIONOYA, Kazuo KUMAGIRI, Takao KUSANO, Makoto YOSHIDA, Masao IKEKAWA, Ichiro KURODA, Takao NISHITANI, "Performance Evaluation of the AV CODEC on a Low-Power SPXK5SC DSP Core" in IEICE TRANSACTIONS on Information,
vol. E88-D, no. 6, pp. 1224-1230, June 2005, doi: 10.1093/ietisy/e88-d.6.1224.
Abstract: This paper provides a performance evaluation of our audio and video CODEC by using a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with a SPXK5SC DSP core in order to evaluate the overall performance of audio/video CODEC on a target system. Our emulation system using a DSP core TEG, which has a bus interface, and an FPGA is suitable for overall system evaluation on real-time workloads as well as architectural investigation. In this paper, we discuss the use of the emulation system in evaluating performance during AV CODEC execution. In addition, an architecture design based on our emulation system is also described.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.6.1224/_p
Copy
@ARTICLE{e88-d_6_1224,
author={Takahiro KUMURA, Norio KAYAMA, Shinichi SHIONOYA, Kazuo KUMAGIRI, Takao KUSANO, Makoto YOSHIDA, Masao IKEKAWA, Ichiro KURODA, Takao NISHITANI, },
journal={IEICE TRANSACTIONS on Information},
title={Performance Evaluation of the AV CODEC on a Low-Power SPXK5SC DSP Core},
year={2005},
volume={E88-D},
number={6},
pages={1224-1230},
abstract={This paper provides a performance evaluation of our audio and video CODEC by using a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with a SPXK5SC DSP core in order to evaluate the overall performance of audio/video CODEC on a target system. Our emulation system using a DSP core TEG, which has a bus interface, and an FPGA is suitable for overall system evaluation on real-time workloads as well as architectural investigation. In this paper, we discuss the use of the emulation system in evaluating performance during AV CODEC execution. In addition, an architecture design based on our emulation system is also described.},
keywords={},
doi={10.1093/ietisy/e88-d.6.1224},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - Performance Evaluation of the AV CODEC on a Low-Power SPXK5SC DSP Core
T2 - IEICE TRANSACTIONS on Information
SP - 1224
EP - 1230
AU - Takahiro KUMURA
AU - Norio KAYAMA
AU - Shinichi SHIONOYA
AU - Kazuo KUMAGIRI
AU - Takao KUSANO
AU - Makoto YOSHIDA
AU - Masao IKEKAWA
AU - Ichiro KURODA
AU - Takao NISHITANI
PY - 2005
DO - 10.1093/ietisy/e88-d.6.1224
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2005
AB - This paper provides a performance evaluation of our audio and video CODEC by using a method for rapidly verifying and evaluating overall performance on real-time workloads of system LSIs integrated with SPXK5SC DSP cores. The SPXK5SC have been developed as a DSP core well-suited to system LSIs. Despite the fact that it is very important to evaluate the overall performance of target LSIs on real workloads before actual LSI fabrication, software simulators are too slow to deal with real workloads and full hardware prototyping is unable to respond well to design improvements. Therefore, we have developed a hardware emulation approach to be used on system LSIs integrated with a SPXK5SC DSP core in order to evaluate the overall performance of audio/video CODEC on a target system. Our emulation system using a DSP core TEG, which has a bus interface, and an FPGA is suitable for overall system evaluation on real-time workloads as well as architectural investigation. In this paper, we discuss the use of the emulation system in evaluating performance during AV CODEC execution. In addition, an architecture design based on our emulation system is also described.
ER -
English
