A 160 mW, 80 nA Standby, MPEG-4 Audiovisual LSI with 16 Mbit Embedded DRAM and a 5 GOPS Post Filtering Unit

Hideho ARAKIDA; Masafumi TAKAHASHI; Yoshiro TSUBOI; Tsuyoshi NISHIKAWA; Hideaki YAMAMOTO; Toshihide FUJIYOSHI; Yoshiyuki KITASHO; Yasuyuki UEDA; Tetsuya FUJITA

A 160 mW, 80 nA Standby, MPEG-4 Audiovisual LSI with 16 Mbit Embedded DRAM and a 5 GOPS Post Filtering Unit

Hideho ARAKIDA, Masafumi TAKAHASHI, Yoshiro TSUBOI, Tsuyoshi NISHIKAWA, Hideaki YAMAMOTO, Toshihide FUJIYOSHI, Yoshiyuki KITASHO, Yasuyuki UEDA, Tetsuya FUJITA

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We present a single-chip MPEG-4 audiovisual LSI in a 0.13 µm CMOS, 5-layer metal technology with 16 Mbit embedded DRAM, which integrates four 16 bit RISC and dedicated hardware accelerators including a 5 GOPS post filtering unit. It consumes 160 mW at 125 MHz and dissipates 80 nA in the standby mode. The chip is the world first LSI handling MPEG-4 CIF video encoding at 15 frames/sec and audio/speech encoding simultaneously.

Publication: IEICE TRANSACTIONS on Electronics Vol.E87-C No.4 pp.475-481

Publication Date: 2004/04/01

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Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)

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Hideho ARAKIDA, Masafumi TAKAHASHI, Yoshiro TSUBOI, Tsuyoshi NISHIKAWA, Hideaki YAMAMOTO, Toshihide FUJIYOSHI, Yoshiyuki KITASHO, Yasuyuki UEDA, Tetsuya FUJITA, "A 160 mW, 80 nA Standby, MPEG-4 Audiovisual LSI with 16 Mbit Embedded DRAM and a 5 GOPS Post Filtering Unit" in IEICE TRANSACTIONS on Electronics, vol. E87-C, no. 4, pp. 475-481, April 2004, doi: .
Abstract: We present a single-chip MPEG-4 audiovisual LSI in a 0.13 µm CMOS, 5-layer metal technology with 16 Mbit embedded DRAM, which integrates four 16 bit RISC and dedicated hardware accelerators including a 5 GOPS post filtering unit. It consumes 160 mW at 125 MHz and dissipates 80 nA in the standby mode. The chip is the world first LSI handling MPEG-4 CIF video encoding at 15 frames/sec and audio/speech encoding simultaneously.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_4_475/_p

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@ARTICLE{e87-c_4_475,
author={Hideho ARAKIDA, Masafumi TAKAHASHI, Yoshiro TSUBOI, Tsuyoshi NISHIKAWA, Hideaki YAMAMOTO, Toshihide FUJIYOSHI, Yoshiyuki KITASHO, Yasuyuki UEDA, Tetsuya FUJITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 160 mW, 80 nA Standby, MPEG-4 Audiovisual LSI with 16 Mbit Embedded DRAM and a 5 GOPS Post Filtering Unit},
year={2004},
volume={E87-C},
number={4},
pages={475-481},
abstract={We present a single-chip MPEG-4 audiovisual LSI in a 0.13 µm CMOS, 5-layer metal technology with 16 Mbit embedded DRAM, which integrates four 16 bit RISC and dedicated hardware accelerators including a 5 GOPS post filtering unit. It consumes 160 mW at 125 MHz and dissipates 80 nA in the standby mode. The chip is the world first LSI handling MPEG-4 CIF video encoding at 15 frames/sec and audio/speech encoding simultaneously.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A 160 mW, 80 nA Standby, MPEG-4 Audiovisual LSI with 16 Mbit Embedded DRAM and a 5 GOPS Post Filtering Unit
T2 - IEICE TRANSACTIONS on Electronics
SP - 475
EP - 481
AU - Hideho ARAKIDA
AU - Masafumi TAKAHASHI
AU - Yoshiro TSUBOI
AU - Tsuyoshi NISHIKAWA
AU - Hideaki YAMAMOTO
AU - Toshihide FUJIYOSHI
AU - Yoshiyuki KITASHO
AU - Yasuyuki UEDA
AU - Tetsuya FUJITA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2004
AB - We present a single-chip MPEG-4 audiovisual LSI in a 0.13 µm CMOS, 5-layer metal technology with 16 Mbit embedded DRAM, which integrates four 16 bit RISC and dedicated hardware accelerators including a 5 GOPS post filtering unit. It consumes 160 mW at 125 MHz and dissipates 80 nA in the standby mode. The chip is the world first LSI handling MPEG-4 CIF video encoding at 15 frames/sec and audio/speech encoding simultaneously.
ER -