IEICE TRANSACTIONS on Electronics
A Single Chip H.32X Multimedia Communication Processor with CIF 30 fr/s MPEG-4/H.26X Bi-directional Codec
Summary :
A single chip processor suitable for various multimedia communication products has been developed. This chip achieves real-time bi-directional encoding/decoding for CIF resolution video at a frame rate of 30 fr/s, and meets such standards, as H.320 and H.324. The chip is composed of a video-processing unit for MPEG-4 and H.26X standards, a DSP unit for speech codec and multiplex processes, and a RISC unit for managing the whole chip. By heterogeneous multiple processor architecture, careful study of task sharing for each processing unit and bus configuration, a single chip solution can be achieved with reasonable operation speed and low-power consumption suitable for consumer products. Moreover, by applying an original video processing unit architecture, this chip achieves real-time bi-directional encoding/decoding for CIF-resolution video at a frame rate of 30 fr/s. An original video bus was developed to provide high performance and low-power consumption while sharing one external memory which is necessary for various video processes and graphics functions. This shared memory also has the effect of minimizing die size and I/O ports. This chip has been fabricated with 4-metal 0.18 µm CMOS technology to produce a chip area of 10.5
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E87-C No.4 pp.482-490
- Publication Date
- 2004/04/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Noriyuki MINEGISHI, Ken-ichi ASANO, Keisuke OKADA, Masahiko YOSHIMOTO, "A Single Chip H.32X Multimedia Communication Processor with CIF 30 fr/s MPEG-4/H.26X Bi-directional Codec" in IEICE TRANSACTIONS on Electronics,
vol. E87-C, no. 4, pp. 482-490, April 2004, doi: .
Abstract: A single chip processor suitable for various multimedia communication products has been developed. This chip achieves real-time bi-directional encoding/decoding for CIF resolution video at a frame rate of 30 fr/s, and meets such standards, as H.320 and H.324. The chip is composed of a video-processing unit for MPEG-4 and H.26X standards, a DSP unit for speech codec and multiplex processes, and a RISC unit for managing the whole chip. By heterogeneous multiple processor architecture, careful study of task sharing for each processing unit and bus configuration, a single chip solution can be achieved with reasonable operation speed and low-power consumption suitable for consumer products. Moreover, by applying an original video processing unit architecture, this chip achieves real-time bi-directional encoding/decoding for CIF-resolution video at a frame rate of 30 fr/s. An original video bus was developed to provide high performance and low-power consumption while sharing one external memory which is necessary for various video processes and graphics functions. This shared memory also has the effect of minimizing die size and I/O ports. This chip has been fabricated with 4-metal 0.18 µm CMOS technology to produce a chip area of 10.5
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e87-c_4_482/_p
Copy
@ARTICLE{e87-c_4_482,
author={Noriyuki MINEGISHI, Ken-ichi ASANO, Keisuke OKADA, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Single Chip H.32X Multimedia Communication Processor with CIF 30 fr/s MPEG-4/H.26X Bi-directional Codec},
year={2004},
volume={E87-C},
number={4},
pages={482-490},
abstract={A single chip processor suitable for various multimedia communication products has been developed. This chip achieves real-time bi-directional encoding/decoding for CIF resolution video at a frame rate of 30 fr/s, and meets such standards, as H.320 and H.324. The chip is composed of a video-processing unit for MPEG-4 and H.26X standards, a DSP unit for speech codec and multiplex processes, and a RISC unit for managing the whole chip. By heterogeneous multiple processor architecture, careful study of task sharing for each processing unit and bus configuration, a single chip solution can be achieved with reasonable operation speed and low-power consumption suitable for consumer products. Moreover, by applying an original video processing unit architecture, this chip achieves real-time bi-directional encoding/decoding for CIF-resolution video at a frame rate of 30 fr/s. An original video bus was developed to provide high performance and low-power consumption while sharing one external memory which is necessary for various video processes and graphics functions. This shared memory also has the effect of minimizing die size and I/O ports. This chip has been fabricated with 4-metal 0.18 µm CMOS technology to produce a chip area of 10.5
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A Single Chip H.32X Multimedia Communication Processor with CIF 30 fr/s MPEG-4/H.26X Bi-directional Codec
T2 - IEICE TRANSACTIONS on Electronics
SP - 482
EP - 490
AU - Noriyuki MINEGISHI
AU - Ken-ichi ASANO
AU - Keisuke OKADA
AU - Masahiko YOSHIMOTO
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E87-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2004
AB - A single chip processor suitable for various multimedia communication products has been developed. This chip achieves real-time bi-directional encoding/decoding for CIF resolution video at a frame rate of 30 fr/s, and meets such standards, as H.320 and H.324. The chip is composed of a video-processing unit for MPEG-4 and H.26X standards, a DSP unit for speech codec and multiplex processes, and a RISC unit for managing the whole chip. By heterogeneous multiple processor architecture, careful study of task sharing for each processing unit and bus configuration, a single chip solution can be achieved with reasonable operation speed and low-power consumption suitable for consumer products. Moreover, by applying an original video processing unit architecture, this chip achieves real-time bi-directional encoding/decoding for CIF-resolution video at a frame rate of 30 fr/s. An original video bus was developed to provide high performance and low-power consumption while sharing one external memory which is necessary for various video processes and graphics functions. This shared memory also has the effect of minimizing die size and I/O ports. This chip has been fabricated with 4-metal 0.18 µm CMOS technology to produce a chip area of 10.5
ER -
English
