IEICE TRANSACTIONS on Fundamentals
Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor
Summary :
Partial forwarding is a design method to place forwarding paths on a part of processor pipeline. Hardware cost of processor can be reduced without performance loss by partial forwarding. However, compiler with the instruction scheduler which considers partial forwarding structure of the target processor is required since conventional scheduling algorithm cannot make the most of partial forwarding structure. In this paper, we propose a heuristic instruction scheduling method for processors with partial forwarding structure. The proposed algorithm uses available distance to schedule instructions which are suitable for the target partial forwarding processor. Experimental results show that the proposed method generates near-optimal solutions in practical time and some of the optimized codes for partial forwarding processor run in the shortest time among the target processors. It also shows that the proposed method is superior to hazard detection unit.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.12 pp.3258-3267
- Publication Date
- 2009/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.3258
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Embedded, Real-Time and Reconfigurable Systems
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Takuji HIEDA, Hiroaki TANAKA, Keishi SAKANUSHI, Yoshinori TAKEUCHI, Masaharu IMAI, "Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3258-3267, December 2009, doi: 10.1587/transfun.E92.A.3258.
Abstract: Partial forwarding is a design method to place forwarding paths on a part of processor pipeline. Hardware cost of processor can be reduced without performance loss by partial forwarding. However, compiler with the instruction scheduler which considers partial forwarding structure of the target processor is required since conventional scheduling algorithm cannot make the most of partial forwarding structure. In this paper, we propose a heuristic instruction scheduling method for processors with partial forwarding structure. The proposed algorithm uses available distance to schedule instructions which are suitable for the target partial forwarding processor. Experimental results show that the proposed method generates near-optimal solutions in practical time and some of the optimized codes for partial forwarding processor run in the shortest time among the target processors. It also shows that the proposed method is superior to hazard detection unit.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3258/_p
Copy
@ARTICLE{e92-a_12_3258,
author={Takuji HIEDA, Hiroaki TANAKA, Keishi SAKANUSHI, Yoshinori TAKEUCHI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor},
year={2009},
volume={E92-A},
number={12},
pages={3258-3267},
abstract={Partial forwarding is a design method to place forwarding paths on a part of processor pipeline. Hardware cost of processor can be reduced without performance loss by partial forwarding. However, compiler with the instruction scheduler which considers partial forwarding structure of the target processor is required since conventional scheduling algorithm cannot make the most of partial forwarding structure. In this paper, we propose a heuristic instruction scheduling method for processors with partial forwarding structure. The proposed algorithm uses available distance to schedule instructions which are suitable for the target partial forwarding processor. Experimental results show that the proposed method generates near-optimal solutions in practical time and some of the optimized codes for partial forwarding processor run in the shortest time among the target processors. It also shows that the proposed method is superior to hazard detection unit.},
keywords={},
doi={10.1587/transfun.E92.A.3258},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3258
EP - 3267
AU - Takuji HIEDA
AU - Hiroaki TANAKA
AU - Keishi SAKANUSHI
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
PY - 2009
DO - 10.1587/transfun.E92.A.3258
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2009
AB - Partial forwarding is a design method to place forwarding paths on a part of processor pipeline. Hardware cost of processor can be reduced without performance loss by partial forwarding. However, compiler with the instruction scheduler which considers partial forwarding structure of the target processor is required since conventional scheduling algorithm cannot make the most of partial forwarding structure. In this paper, we propose a heuristic instruction scheduling method for processors with partial forwarding structure. The proposed algorithm uses available distance to schedule instructions which are suitable for the target partial forwarding processor. Experimental results show that the proposed method generates near-optimal solutions in practical time and some of the optimized codes for partial forwarding processor run in the shortest time among the target processors. It also shows that the proposed method is superior to hazard detection unit.
ER -
English
