IEICE TRANSACTIONS on Fundamentals
Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation
Summary :
Symmetry constrains are the constraints that the given cells should be placed symmetrically in design of analog ICs. We use O-tree to represent placements and propose a decoding algorithm which can obtain one of the minimum placements satisfying the constraints. The decoding algorithm uses linear programming, which is too much time consuming. Therefore we propose a graph based method to recognize if there exists no placement satisfying both the given symmetry and O-tree constraints, and use the method before application of linear programming. The effectiveness of the proposed method was shown by computational experiments.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.2 pp.467-474
- Publication Date
- 2009/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.467
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Natsumi HIRAKAWA, Kunihiro FUJIYOSHI, "Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 2, pp. 467-474, February 2009, doi: 10.1587/transfun.E92.A.467.
Abstract: Symmetry constrains are the constraints that the given cells should be placed symmetrically in design of analog ICs. We use O-tree to represent placements and propose a decoding algorithm which can obtain one of the minimum placements satisfying the constraints. The decoding algorithm uses linear programming, which is too much time consuming. Therefore we propose a graph based method to recognize if there exists no placement satisfying both the given symmetry and O-tree constraints, and use the method before application of linear programming. The effectiveness of the proposed method was shown by computational experiments.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.467/_p
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@ARTICLE{e92-a_2_467,
author={Natsumi HIRAKAWA, Kunihiro FUJIYOSHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation},
year={2009},
volume={E92-A},
number={2},
pages={467-474},
abstract={Symmetry constrains are the constraints that the given cells should be placed symmetrically in design of analog ICs. We use O-tree to represent placements and propose a decoding algorithm which can obtain one of the minimum placements satisfying the constraints. The decoding algorithm uses linear programming, which is too much time consuming. Therefore we propose a graph based method to recognize if there exists no placement satisfying both the given symmetry and O-tree constraints, and use the method before application of linear programming. The effectiveness of the proposed method was shown by computational experiments.},
keywords={},
doi={10.1587/transfun.E92.A.467},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 467
EP - 474
AU - Natsumi HIRAKAWA
AU - Kunihiro FUJIYOSHI
PY - 2009
DO - 10.1587/transfun.E92.A.467
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2009
AB - Symmetry constrains are the constraints that the given cells should be placed symmetrically in design of analog ICs. We use O-tree to represent placements and propose a decoding algorithm which can obtain one of the minimum placements satisfying the constraints. The decoding algorithm uses linear programming, which is too much time consuming. Therefore we propose a graph based method to recognize if there exists no placement satisfying both the given symmetry and O-tree constraints, and use the method before application of linear programming. The effectiveness of the proposed method was shown by computational experiments.
ER -
English
