High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders

Kyo TAKAHASHI; Shingo SATO; Tadamichi KUDO; Yoshitaka TSUNEKAWA

doi:10.1587/transfun.E92.A.633

High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders

Kyo TAKAHASHI, Shingo SATO, Tadamichi KUDO, Yoshitaka TSUNEKAWA

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In this report, we propose a high-performance pipelined VLSI architecture of the LMS adaptive filter derived by a cut-set retiming technique. The proposed architecture has a peculiar pipelined form with 3 adaptation delays, and the FIR filter portion has a peculiar class of the transposed form providing a minimum output latency and coefficient delay. Both the delays, the adaptation delay and coefficient delay, are compensated by a look-ahead conversion. A new high-speed 4-input and 2-output CSA type adder with a small hardware is employed. The proposed architecture can achieve a good convergence property, high-sampling rate, minimum output latency, small hardware, and lower power dissipation, simultaneously, and is very suitable to implement on the VLSI.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.2 pp.633-637

Publication Date: 2009/02/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E92.A.633

Type of Manuscript: LETTER

Category: Digital Signal Processing

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Kyo TAKAHASHI, Shingo SATO, Tadamichi KUDO, Yoshitaka TSUNEKAWA, "High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders" in IEICE TRANSACTIONS on Fundamentals, vol. E92-A, no. 2, pp. 633-637, February 2009, doi: 10.1587/transfun.E92.A.633.
Abstract: In this report, we propose a high-performance pipelined VLSI architecture of the LMS adaptive filter derived by a cut-set retiming technique. The proposed architecture has a peculiar pipelined form with 3 adaptation delays, and the FIR filter portion has a peculiar class of the transposed form providing a minimum output latency and coefficient delay. Both the delays, the adaptation delay and coefficient delay, are compensated by a look-ahead conversion. A new high-speed 4-input and 2-output CSA type adder with a small hardware is employed. The proposed architecture can achieve a good convergence property, high-sampling rate, minimum output latency, small hardware, and lower power dissipation, simultaneously, and is very suitable to implement on the VLSI.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.633/_p

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@ARTICLE{e92-a_2_633,
author={Kyo TAKAHASHI, Shingo SATO, Tadamichi KUDO, Yoshitaka TSUNEKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders},
year={2009},
volume={E92-A},
number={2},
pages={633-637},
abstract={In this report, we propose a high-performance pipelined VLSI architecture of the LMS adaptive filter derived by a cut-set retiming technique. The proposed architecture has a peculiar pipelined form with 3 adaptation delays, and the FIR filter portion has a peculiar class of the transposed form providing a minimum output latency and coefficient delay. Both the delays, the adaptation delay and coefficient delay, are compensated by a look-ahead conversion. A new high-speed 4-input and 2-output CSA type adder with a small hardware is employed. The proposed architecture can achieve a good convergence property, high-sampling rate, minimum output latency, small hardware, and lower power dissipation, simultaneously, and is very suitable to implement on the VLSI.},
keywords={},
doi={10.1587/transfun.E92.A.633},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - High-Performance VLSI Architecture of the LMS Adaptive Filter Using 4-2 Adders
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 633
EP - 637
AU - Kyo TAKAHASHI
AU - Shingo SATO
AU - Tadamichi KUDO
AU - Yoshitaka TSUNEKAWA
PY - 2009
DO - 10.1587/transfun.E92.A.633
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2009
AB - In this report, we propose a high-performance pipelined VLSI architecture of the LMS adaptive filter derived by a cut-set retiming technique. The proposed architecture has a peculiar pipelined form with 3 adaptation delays, and the FIR filter portion has a peculiar class of the transposed form providing a minimum output latency and coefficient delay. Both the delays, the adaptation delay and coefficient delay, are compensated by a look-ahead conversion. A new high-speed 4-input and 2-output CSA type adder with a small hardware is employed. The proposed architecture can achieve a good convergence property, high-sampling rate, minimum output latency, small hardware, and lower power dissipation, simultaneously, and is very suitable to implement on the VLSI.
ER -