IEICE TRANSACTIONS on Fundamentals
A Processor Accelerator for Software Decoding of BCH Codes
Summary :
The BCH code is one of the well-known error correction codes and its decoding contains many operations in Galois field. These operations require many instruction steps or large memory area for look-up tables on ordinary processors. While dedicated hardware BCH decoders achieves higher decoding speed than software, the advantage of software decoding is its flexibility to decode BCH codes of variable parameters. In this paper, an auxiliary circuit to be embedded in a pipelined processor is proposed which accelerates software decoding of various BCH codes.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.7 pp.1329-1337
- Publication Date
- 2010/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.1329
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Kazuhito ITO, "A Processor Accelerator for Software Decoding of BCH Codes" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 7, pp. 1329-1337, July 2010, doi: 10.1587/transfun.E93.A.1329.
Abstract: The BCH code is one of the well-known error correction codes and its decoding contains many operations in Galois field. These operations require many instruction steps or large memory area for look-up tables on ordinary processors. While dedicated hardware BCH decoders achieves higher decoding speed than software, the advantage of software decoding is its flexibility to decode BCH codes of variable parameters. In this paper, an auxiliary circuit to be embedded in a pipelined processor is proposed which accelerates software decoding of various BCH codes.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1329/_p
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@ARTICLE{e93-a_7_1329,
author={Kazuhito ITO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Processor Accelerator for Software Decoding of BCH Codes},
year={2010},
volume={E93-A},
number={7},
pages={1329-1337},
abstract={The BCH code is one of the well-known error correction codes and its decoding contains many operations in Galois field. These operations require many instruction steps or large memory area for look-up tables on ordinary processors. While dedicated hardware BCH decoders achieves higher decoding speed than software, the advantage of software decoding is its flexibility to decode BCH codes of variable parameters. In this paper, an auxiliary circuit to be embedded in a pipelined processor is proposed which accelerates software decoding of various BCH codes.},
keywords={},
doi={10.1587/transfun.E93.A.1329},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - A Processor Accelerator for Software Decoding of BCH Codes
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1329
EP - 1337
AU - Kazuhito ITO
PY - 2010
DO - 10.1587/transfun.E93.A.1329
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2010
AB - The BCH code is one of the well-known error correction codes and its decoding contains many operations in Galois field. These operations require many instruction steps or large memory area for look-up tables on ordinary processors. While dedicated hardware BCH decoders achieves higher decoding speed than software, the advantage of software decoding is its flexibility to decode BCH codes of variable parameters. In this paper, an auxiliary circuit to be embedded in a pipelined processor is proposed which accelerates software decoding of various BCH codes.
ER -
English
