In this paper, we propose a novel data hiding technique for G.711-coded speech based on the LSB substitution method. The novel feature of the proposed method is that a low-bitrate encoder, G.726 ADPCM, is used as a reference for deciding how many bits can be embedded in a sample. Experiments showed that the method outperformed the simple LSB substitution method and the selective embedding method proposed by Aoki. We achieved 4-kbit/s embedding with almost no subjective degradation of speech quality, and 10 kbit/s while maintaining good quality.

At some point in a digital communications receiver, the received analog signal must be sampled. Good performance requires that these samples be taken at the right times. The process of synchronizing the sampler with the received analog waveform is known as timing recovery. Conventional timing recovery techniques perform well only when operating at high signal-to-noise ratio (SNR). Nonetheless, iterative error-control codes allow reliable communication at very low SNR, where conventional techniques fail. This paper provides a detailed review on the timing recovery strategies based on per-survivor processing (PSP) that are capable of working at low SNR. We also investigate their performance in magnetic recording systems because magnetic recording is a primary method of storage for a variety of applications, including desktop, mobile, and server systems. Results indicate that the timing recovery strategies based on PSP perform better than the conventional ones and are thus worth being employed in magnetic recording systems.

In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.

Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.

We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8 bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12 bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2 Mλ² area with 35 bits of SRAM, and the prototype SSFPGA with 3430 (1020) blocks is designed and fabricated using 65 nm CMOS. Measured results show at 1.2 V 430 MHz and 647 MHz operation for a 3 bit ripple carry adder, without and with throughput optimization, respectively. We find that using the proposed pipeline alignment techniques we can perform at maximum throughput of 647 MHz in various benchmarks on the SSFPGA. We demonstrate up to 56.1 times throughput improvement with our pipeline alignment techniques. The pipeline alignment is carried out within the number of logic elements in the array and pipeline buffers in the switching matrix.

The BCH code is one of the well-known error correction codes and its decoding contains many operations in Galois field. These operations require many instruction steps or large memory area for look-up tables on ordinary processors. While dedicated hardware BCH decoders achieves higher decoding speed than software, the advantage of software decoding is its flexibility to decode BCH codes of variable parameters. In this paper, an auxiliary circuit to be embedded in a pipelined processor is proposed which accelerates software decoding of various BCH codes.

This paper aims at analyzing the performance of an anonymous communication system 3-Mode Net with respect to the number of relay nodes required for communication and sender anonymity. As for the number of relay nodes, we give explicit formulas of the probability distribution, the expectation, and the variance. Considering sender anonymity, we quantify the degree of sender anonymity under a situation where some relay nodes collude with each other. The above analyses use random walk theory, a probability generating function, and their properties. From obtained formulas, we show several conditions for avoiding a situation where the number of relay nodes becomes large, and for providing high sender anonymity. Furthermore, we investigate the relationship between the number of relay nodes and sender anonymity, and give a condition for providing a better performance of 3 MN.

We propose a randomness test based on the T-complexity of a sequence, which can be calculated using a parsing algorithm called T-decomposition. Recently, the Lempel-Ziv (LZ) randomness test based on LZ-complexity using the LZ78 incremental parsing was officially excluded from the NIST test suite in NIST SP 800-22. This is caused from the problem that the distribution of P-values for random sequences of length 10⁶ is strictly discrete for the LZ-complexity. Our proposed test can overcome this problem because T-complexity has almost ideal continuous distribution of P-values for random sequences of length 10⁶. We also devise a new sequential T-decomposition algorithm using forward parsing, while the original T-decomposition is an off-line algorithm using backward parsing. Our proposed test can become a supplement to NIST SP 800-22 because it can detect several undesirable pseudo-random numbers that the NIST test suite almost fails to detect.

Universal Slepian-Wolf coding for parametric general sources is considered. Our main result shows that under mild conditions on the family of sources, there exists a universal decoder that attains asymptotically the same random-coding error exponent as the maximum-likelihood decoder.

Integer codes are very flexible and can be applied in different modulation schemes. A soft decoding algorithm for integer codes will be introduced. Comparison of symbol error probability (SEP) versus signal-to-noise ratio (SNR) between soft and hard decoding using integer coded modulation shows us that we can obtain at least 2 dB coding gain. Also, we shall compare our results with trellis coded modulation (TCM) because of their similar decoding schemes and complexity.

Detection of transient signals is generally done by examining power and spectral variation of the received signal, but it becomes a difficult task when the background noise gets large. In this paper, we propose a robust transient detection algorithm using the EVRC noise suppression module. We define new parameters from the outputs of the EVRC noise suppression module for transient detection. Experimental results with various types of underwater transients have shown that the proposed method outperforms the conventional energy-based method and achieved performance improvement of detection rate by 7% to 15% for various types of background noise.

This letter addresses the edge effect on a windowed discrete Fourier transform (WDFT)-based channel estimator for orthogonal frequency division multiplexing (OFDM) systems with virtual carriers in non-sample spaced channels and derives a sufficient condition to reduce the edge effect. Moreover, a modified WDFT-based channel estimator with multi-step linear prediction as an edge effect reduction technique is proposed. Simulation results show that it offers around 5 dB signal-to-noise ratio (SNR) gain over the conventional WDFT-based channel estimator at bit error rate (BER) of 10^-3.

In this letter, we propose a novel approach to human activity recognition. We present a class of features that are robust to the tilt of the attached sensor module and a state transition model suitable for HMM-based activity recognition. In addition, postprocessing techniques are applied to stabilize the recognition results. The proposed approach shows significant improvements in recognition experiments over a variety of human activity DB.

In this letter, delay-dependent stability criterion for linear time-delay systems with multiple time varying delays is proposed by employing the Lyapunov-Krasovskii functional approach and integral inequality. By the N-segmentation of delay length, we obtain less conservative results on the delay bounds which guarantee the asymptotic stability of the linear time-delay systems with multiple time varying delays. Simulation results show that the proposed stability criteria are less conservative than several other existing criteria.

This paper presents a novel parallel boost converter using switched capacitors The switches are controlled not only by periodic clock but also by voltage-mode threshold that is a key to realize strong stability, fast transient and variable output. The dynamics is described by a piecewise linear equation, the mapping procedure is applicable and the system operation can be analyzed precisely.

Multi-dimensional (MD) periodic complementary array sets (CASs) with impulse-like MD periodic autocorrelation function are naturally generalized to (one dimensional) periodic complementary sequence sets, and such array sets are widely applied to communication, radar, sonar, coded aperture imaging, and so forth. In this letter, based on multi-dimensional perfect arrays (MD PAs), a method for constructing MD periodic CASs is presented, which is carried out by sampling MD PAs. It is particularly worth mentioning that the numbers and sizes of sub-arrays in the proposed MD periodic CASs can be freely changed within the range of possibilities. In particular, for arbitrarily given positive integers M and L, two-dimensional periodic polyphase CASs with the number M² and size L L of sub-arrays can be produced by the proposed method. And analogously, pseudo-random MD periodic CASs can be given when pseudo-random MD arrays are sampled. Finally, the proposed method's validity is made sure by a given example.