A Study of Capture-Safe Test Generation Flow for At-Speed Testing
Summary :
Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.7 pp.1309-1318
- Publication Date
- 2010/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.1309
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Kohei MIYASE
Xiaoqing WEN
Seiji KAJIHARA
Yuta YAMATO
Atsushi TAKASHIMA
Hiroshi FURUKAWA
Kenji NODA
Hideaki ITO
Kazumi HATAYAMA
Takashi AIKYO
Kewal K. SALUJA
Keyword
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Kohei MIYASE, Xiaoqing WEN, Seiji KAJIHARA, Yuta YAMATO, Atsushi TAKASHIMA, Hiroshi FURUKAWA, Kenji NODA, Hideaki ITO, Kazumi HATAYAMA, Takashi AIKYO, Kewal K. SALUJA, "A Study of Capture-Safe Test Generation Flow for At-Speed Testing" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 7, pp. 1309-1318, July 2010, doi: 10.1587/transfun.E93.A.1309.
Abstract: Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1309/_p
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@ARTICLE{e93-a_7_1309,
author={Kohei MIYASE, Xiaoqing WEN, Seiji KAJIHARA, Yuta YAMATO, Atsushi TAKASHIMA, Hiroshi FURUKAWA, Kenji NODA, Hideaki ITO, Kazumi HATAYAMA, Takashi AIKYO, Kewal K. SALUJA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Study of Capture-Safe Test Generation Flow for At-Speed Testing},
year={2010},
volume={E93-A},
number={7},
pages={1309-1318},
abstract={Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.},
keywords={},
doi={10.1587/transfun.E93.A.1309},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - A Study of Capture-Safe Test Generation Flow for At-Speed Testing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1309
EP - 1318
AU - Kohei MIYASE
AU - Xiaoqing WEN
AU - Seiji KAJIHARA
AU - Yuta YAMATO
AU - Atsushi TAKASHIMA
AU - Hiroshi FURUKAWA
AU - Kenji NODA
AU - Hideaki ITO
AU - Kazumi HATAYAMA
AU - Takashi AIKYO
AU - Kewal K. SALUJA
PY - 2010
DO - 10.1587/transfun.E93.A.1309
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2010
AB - Capture-safety, (defined as the avoidance of timing error due to unduly high launch switching activity in capture mode during at-speed scan testing), is critical in avoiding test induced yield loss. Although several sophisticated techniques are available for reducing capture IR-drop, there are few complete capture-safe test generation flows. This paper addresses the problem by proposing a novel and practical capture-safe test generation flow, featuring (1) a complete capture-safe test generation flow; (2) reliable capture-safety checking; and (3) effective capture-safety improvement by combining X-bit identification & X-filling with low launch-switching-activity test generation. The proposed flow minimizes test data inflation and is compatible with existing automatic test pattern generation (ATPG) flow. The techniques proposed in the flow achieve capture-safety without changing the circuit-under-test or the clocking scheme.
ER -
English
