A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue
Summary :
In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 µm standard CMOS process, the LDPC decoder has an area of 12.51 mm2. The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.8 pp.1415-1424
- Publication Date
- 2010/08/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.1415
- Type of Manuscript
- Special Section PAPER (Special Section on Signal Processing)
- Category
- Digital Signal Processing
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Keyword
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Yan YING, Dan BAO, Zhiyi YU, Xiaoyang ZENG, Yun CHEN, "A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 8, pp. 1415-1424, August 2010, doi: 10.1587/transfun.E93.A.1415.
Abstract: In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 µm standard CMOS process, the LDPC decoder has an area of 12.51 mm2. The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1415/_p
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@ARTICLE{e93-a_8_1415,
author={Yan YING, Dan BAO, Zhiyi YU, Xiaoyang ZENG, Yun CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue},
year={2010},
volume={E93-A},
number={8},
pages={1415-1424},
abstract={In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 µm standard CMOS process, the LDPC decoder has an area of 12.51 mm2. The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.},
keywords={},
doi={10.1587/transfun.E93.A.1415},
ISSN={1745-1337},
month={August},}
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TY - JOUR
TI - A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1415
EP - 1424
AU - Yan YING
AU - Dan BAO
AU - Zhiyi YU
AU - Xiaoyang ZENG
AU - Yun CHEN
PY - 2010
DO - 10.1587/transfun.E93.A.1415
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2010
AB - In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 µm standard CMOS process, the LDPC decoder has an area of 12.51 mm2. The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.
ER -
English
