In this paper, we proposed the compact construction of a matched filter for integrand code, which do not require the high-rate clock pulse in two-valued PWM (pulse width modulation) code, using a real-valued shift-orthogonal finite-length sequence, which has a sharp aperiodic autocorrelation function with zero sidelobes except at left and right shift-ends. This matched filters are implemented on a field programmable gate array (FPGA) corresponding to 400,000 logic gates. A proposed matched filter for the sequence of length 129 can be constructed by the circuit scale of about 47% compared with conventional filter.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Takahiro MATSUMOTO, "Compact Matched Filter for Integrand Code Using a Real-Valued Shift-Orthogonal Finite-Length Sequence" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 11, pp. 2328-2331, November 2010, doi: 10.1587/transfun.E93.A.2328.
Abstract: In this paper, we proposed the compact construction of a matched filter for integrand code, which do not require the high-rate clock pulse in two-valued PWM (pulse width modulation) code, using a real-valued shift-orthogonal finite-length sequence, which has a sharp aperiodic autocorrelation function with zero sidelobes except at left and right shift-ends. This matched filters are implemented on a field programmable gate array (FPGA) corresponding to 400,000 logic gates. A proposed matched filter for the sequence of length 129 can be constructed by the circuit scale of about 47% compared with conventional filter.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2328/_p
Copy
@ARTICLE{e93-a_11_2328,
author={Takahiro MATSUMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Compact Matched Filter for Integrand Code Using a Real-Valued Shift-Orthogonal Finite-Length Sequence},
year={2010},
volume={E93-A},
number={11},
pages={2328-2331},
abstract={In this paper, we proposed the compact construction of a matched filter for integrand code, which do not require the high-rate clock pulse in two-valued PWM (pulse width modulation) code, using a real-valued shift-orthogonal finite-length sequence, which has a sharp aperiodic autocorrelation function with zero sidelobes except at left and right shift-ends. This matched filters are implemented on a field programmable gate array (FPGA) corresponding to 400,000 logic gates. A proposed matched filter for the sequence of length 129 can be constructed by the circuit scale of about 47% compared with conventional filter.},
keywords={},
doi={10.1587/transfun.E93.A.2328},
ISSN={1745-1337},
month={November},}
Copy
TY - JOUR
TI - Compact Matched Filter for Integrand Code Using a Real-Valued Shift-Orthogonal Finite-Length Sequence
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2328
EP - 2331
AU - Takahiro MATSUMOTO
PY - 2010
DO - 10.1587/transfun.E93.A.2328
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2010
AB - In this paper, we proposed the compact construction of a matched filter for integrand code, which do not require the high-rate clock pulse in two-valued PWM (pulse width modulation) code, using a real-valued shift-orthogonal finite-length sequence, which has a sharp aperiodic autocorrelation function with zero sidelobes except at left and right shift-ends. This matched filters are implemented on a field programmable gate array (FPGA) corresponding to 400,000 logic gates. A proposed matched filter for the sequence of length 129 can be constructed by the circuit scale of about 47% compared with conventional filter.
ER -