IEICE TRANSACTIONS on Fundamentals
Gate Delay Estimation in STA under Dynamic Power Supply Noise
Summary :
This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 1% error on average.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.12 pp.2447-2455
- Publication Date
- 2010/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.2447
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
Authors
Keyword
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Takaaki OKUMURA, Fumihiro MINAMI, Kenji SHIMAZAKI, Kimihiko KUWADA, Masanori HASHIMOTO, "Gate Delay Estimation in STA under Dynamic Power Supply Noise" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2447-2455, December 2010, doi: 10.1587/transfun.E93.A.2447.
Abstract: This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 1% error on average.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2447/_p
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@ARTICLE{e93-a_12_2447,
author={Takaaki OKUMURA, Fumihiro MINAMI, Kenji SHIMAZAKI, Kimihiko KUWADA, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Gate Delay Estimation in STA under Dynamic Power Supply Noise},
year={2010},
volume={E93-A},
number={12},
pages={2447-2455},
abstract={This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 1% error on average.},
keywords={},
doi={10.1587/transfun.E93.A.2447},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Gate Delay Estimation in STA under Dynamic Power Supply Noise
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2447
EP - 2455
AU - Takaaki OKUMURA
AU - Fumihiro MINAMI
AU - Kenji SHIMAZAKI
AU - Kimihiko KUWADA
AU - Masanori HASHIMOTO
PY - 2010
DO - 10.1587/transfun.E93.A.2447
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 1% error on average.
ER -
English
