IEICE TRANSACTIONS on Fundamentals
A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS
Summary :
A 9-bit 100-MS/s successive approximation register (SAR) ADC with low power and small area has been implemented in 65-nm CMOS technology. A tri-level charge redistribution technique is proposed to reduce DAC switching energy and settling time. By connecting bottom plates of differential capacitor arrays for charge sharing, extra reference voltage is avoided. Two reference voltages charging and discharging the capacitors are chosen to be supply voltage and ground in order to save energy and achieve a rail-to-rail input range. Split capacitor arrays with mismatch calibration are implemented for small area and small input capacitance without linearity degradation. The ADC achieves a peak SNDR of 53.1 dB and consumes 1.46 mW from a 1.2-V supply, resulting in a figure of merit (FOM) of 39 fJ/conversion-step. The total active area is 0.012 mm2 and the input capacitance is 180 fF.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.12 pp.2600-2608
- Publication Date
- 2010/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.2600
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Circuit Design
Authors
Keyword
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Yanfei CHEN, Sanroku TSUKAMOTO, Tadahiro KURODA, "A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2600-2608, December 2010, doi: 10.1587/transfun.E93.A.2600.
Abstract: A 9-bit 100-MS/s successive approximation register (SAR) ADC with low power and small area has been implemented in 65-nm CMOS technology. A tri-level charge redistribution technique is proposed to reduce DAC switching energy and settling time. By connecting bottom plates of differential capacitor arrays for charge sharing, extra reference voltage is avoided. Two reference voltages charging and discharging the capacitors are chosen to be supply voltage and ground in order to save energy and achieve a rail-to-rail input range. Split capacitor arrays with mismatch calibration are implemented for small area and small input capacitance without linearity degradation. The ADC achieves a peak SNDR of 53.1 dB and consumes 1.46 mW from a 1.2-V supply, resulting in a figure of merit (FOM) of 39 fJ/conversion-step. The total active area is 0.012 mm2 and the input capacitance is 180 fF.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2600/_p
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@ARTICLE{e93-a_12_2600,
author={Yanfei CHEN, Sanroku TSUKAMOTO, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS},
year={2010},
volume={E93-A},
number={12},
pages={2600-2608},
abstract={A 9-bit 100-MS/s successive approximation register (SAR) ADC with low power and small area has been implemented in 65-nm CMOS technology. A tri-level charge redistribution technique is proposed to reduce DAC switching energy and settling time. By connecting bottom plates of differential capacitor arrays for charge sharing, extra reference voltage is avoided. Two reference voltages charging and discharging the capacitors are chosen to be supply voltage and ground in order to save energy and achieve a rail-to-rail input range. Split capacitor arrays with mismatch calibration are implemented for small area and small input capacitance without linearity degradation. The ADC achieves a peak SNDR of 53.1 dB and consumes 1.46 mW from a 1.2-V supply, resulting in a figure of merit (FOM) of 39 fJ/conversion-step. The total active area is 0.012 mm2 and the input capacitance is 180 fF.},
keywords={},
doi={10.1587/transfun.E93.A.2600},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2600
EP - 2608
AU - Yanfei CHEN
AU - Sanroku TSUKAMOTO
AU - Tadahiro KURODA
PY - 2010
DO - 10.1587/transfun.E93.A.2600
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - A 9-bit 100-MS/s successive approximation register (SAR) ADC with low power and small area has been implemented in 65-nm CMOS technology. A tri-level charge redistribution technique is proposed to reduce DAC switching energy and settling time. By connecting bottom plates of differential capacitor arrays for charge sharing, extra reference voltage is avoided. Two reference voltages charging and discharging the capacitors are chosen to be supply voltage and ground in order to save energy and achieve a rail-to-rail input range. Split capacitor arrays with mismatch calibration are implemented for small area and small input capacitance without linearity degradation. The ADC achieves a peak SNDR of 53.1 dB and consumes 1.46 mW from a 1.2-V supply, resulting in a figure of merit (FOM) of 39 fJ/conversion-step. The total active area is 0.012 mm2 and the input capacitance is 180 fF.
ER -
English
