IEICE TRANSACTIONS on Fundamentals
Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise
Summary :
This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold times on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time, and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.10 pp.1948-1953
- Publication Date
- 2011/10/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.1948
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Takaaki OKUMURA, Masanori HASHIMOTO, "Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 10, pp. 1948-1953, October 2011, doi: 10.1587/transfun.E94.A.1948.
Abstract: This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold times on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time, and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.1948/_p
Copy
@ARTICLE{e94-a_10_1948,
author={Takaaki OKUMURA, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise},
year={2011},
volume={E94-A},
number={10},
pages={1948-1953},
abstract={This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold times on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time, and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.},
keywords={},
doi={10.1587/transfun.E94.A.1948},
ISSN={1745-1337},
month={October},}
Copy
TY - JOUR
TI - Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1948
EP - 1953
AU - Takaaki OKUMURA
AU - Masanori HASHIMOTO
PY - 2011
DO - 10.1587/transfun.E94.A.1948
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2011
AB - This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold times on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time, and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.
ER -
English
